Merge pull request #1856 from masahisak/synquacer-scmi-support
plat/synquacer: enable SCMI support
This commit is contained in:
Soby Mathew
GitHub
commit
eb9da9e182
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@ -152,4 +152,9 @@ static inline void validate_scmi_channel(scmi_channel_t *ch)
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assert(ch->info && ch->info->scmi_mbx_mem);
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}
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/*
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* SCMI vendor specific protocol
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*/
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#define SCMI_SYS_VENDOR_EXT_PROTO_ID 0x80
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#endif /* SCMI_PRIVATE_H */
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@ -0,0 +1,60 @@
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/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/arm/css/scmi.h>
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#include "scmi_private.h"
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#include "scmi_sq.h"
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#include <sq_common.h>
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/* SCMI messge ID to get the available DRAM region */
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#define SCMI_VENDOR_EXT_MEMINFO_GET_MSG 0x3
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/*
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* API to get the available DRAM region
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*/
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int scmi_get_draminfo(void *p, struct draminfo *info)
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{
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mailbox_mem_t *mbx_mem;
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int token = 0, ret;
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scmi_channel_t *ch = (scmi_channel_t *)p;
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struct dram_info_resp response;
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validate_scmi_channel(ch);
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scmi_get_channel(ch);
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mbx_mem = (mailbox_mem_t *)(ch->info->scmi_mbx_mem);
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mbx_mem->msg_header = SCMI_MSG_CREATE(SCMI_SYS_VENDOR_EXT_PROTO_ID,
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SCMI_VENDOR_EXT_MEMINFO_GET_MSG, token);
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mbx_mem->len = 8;
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mbx_mem->flags = SCMI_FLAG_RESP_POLL;
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scmi_send_sync_command(ch);
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/*
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* Ensure that any read to the SCPI payload area is done after reading
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* the MHU register. If these 2 reads were reordered then the CPU would
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* read invalid payload data
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*/
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dmbld();
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/* Get the return values */
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SCMI_PAYLOAD_RET_VAL1(mbx_mem->payload, ret);
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memcpy(&response, (void *)mbx_mem->payload, sizeof(response));
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scmi_put_channel(ch);
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*info = response.info;
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return ret;
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}
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@ -0,0 +1,25 @@
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/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SCMI_SQ_H
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#define SCMI_SQ_H
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#include <stddef.h>
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#include <stdint.h>
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#include <sq_common.h>
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/* Structure to represent available DRAM region */
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struct dram_info_resp {
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int status;
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int reserved;
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struct draminfo info;
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};
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/* API to get the available DRAM region */
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int scmi_get_draminfo(void *p, struct draminfo *info);
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#endif /* SCMI_SQ_H */
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@ -12,7 +12,7 @@
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#include <lib/mmio.h>
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/* MHUv2 Base Address */
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#define MHUV2_BASE_ADDR PLAT_CSS_MHU_BASE
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#define MHUV2_BASE_ADDR PLAT_MHUV2_BASE
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/* MHUv2 Control Registers Offsets */
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#define MHU_V2_MSG_NO_CAP_OFFSET 0xF80
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@ -222,6 +222,7 @@
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/* MHU related constants */
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#define PLAT_CSS_MHU_BASE UL(0x2b1f0000)
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#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
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/*
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* Base address of the first memory region used for communication between AP
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@ -61,6 +61,7 @@
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#define PLAT_ARM_NSTIMER_FRAME_ID 0
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#define PLAT_CSS_MHU_BASE 0x45000000
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#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
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#define PLAT_MAX_PWR_LVL 1
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#define PLAT_ARM_G1S_IRQS ARM_G1S_IRQS, \
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@ -16,6 +16,7 @@
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#define CSS_SGI_MAX_PE_PER_CPU 2
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#define PLAT_CSS_MHU_BASE UL(0x45400000)
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#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
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/* Base address of DMC-620 instances */
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#define RDE1EDGE_DMC620_BASE0 UL(0x4e000000)
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@ -16,6 +16,7 @@
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#define CSS_SGI_MAX_PE_PER_CPU 1
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#define PLAT_CSS_MHU_BASE UL(0x45400000)
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#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
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/* Base address of DMC-620 instances */
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#define RDN1EDGE_DMC620_BASE0 UL(0x4e000000)
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@ -16,6 +16,7 @@
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#define CSS_SGI_MAX_PE_PER_CPU 1
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#define PLAT_CSS_MHU_BASE UL(0x45000000)
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#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
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/* Base address of DMC-620 instances */
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#define SGI575_DMC620_BASE0 UL(0x4e000000)
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@ -86,6 +86,7 @@
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/* MHU related constants */
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#define PLAT_CSS_MHU_BASE 0x2b1f0000
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#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
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#define PLAT_ARM_TRUSTED_ROM_BASE 0x00000000
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#define PLAT_ARM_TRUSTED_ROM_SIZE 0x00080000
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@ -0,0 +1,239 @@
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/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <string.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/arm/css/css_mhu_doorbell.h>
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#include <drivers/arm/css/css_scp.h>
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#include <drivers/arm/css/scmi.h>
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#include <plat/arm/css/common/css_pm.h>
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#include <plat/common/platform.h>
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#include <platform_def.h>
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#include <scmi_sq.h>
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#include <sq_common.h>
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/*
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* This file implements the SCP helper functions using SCMI protocol.
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*/
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DEFINE_BAKERY_LOCK(sq_scmi_lock);
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#define SQ_SCMI_LOCK_GET_INSTANCE (&sq_scmi_lock)
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#define SQ_SCMI_PAYLOAD_BASE PLAT_SQ_SCP_COM_SHARED_MEM_BASE
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#define MHU_CPU_INTR_S_SET_OFFSET 0x308
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const uint32_t sq_core_pos_to_scmi_dmn_id_map[PLATFORM_CORE_COUNT] = {
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0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11,
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12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23
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};
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static scmi_channel_plat_info_t sq_scmi_plat_info = {
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.scmi_mbx_mem = SQ_SCMI_PAYLOAD_BASE,
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.db_reg_addr = PLAT_SQ_MHU_BASE + MHU_CPU_INTR_S_SET_OFFSET,
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.db_preserve_mask = 0xfffffffe,
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.db_modify_mask = 0x1,
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.ring_doorbell = &mhu_ring_doorbell,
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};
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/*
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* SCMI power state parameter bit field encoding for SynQuacer platform.
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*
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* 31 20 19 16 15 12 11 8 7 4 3 0
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* +-------------------------------------------------------------+
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* | SBZ | Max level | Level 3 | Level 2 | Level 1 | Level 0 |
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* | | | state | state | state | state |
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* +-------------------------------------------------------------+
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*
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* `Max level` encodes the highest level that has a valid power state
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* encoded in the power state.
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*/
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#define SCMI_PWR_STATE_MAX_PWR_LVL_SHIFT 16
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#define SCMI_PWR_STATE_MAX_PWR_LVL_WIDTH 4
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#define SCMI_PWR_STATE_MAX_PWR_LVL_MASK \
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((1 << SCMI_PWR_STATE_MAX_PWR_LVL_WIDTH) - 1)
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#define SCMI_SET_PWR_STATE_MAX_PWR_LVL(_power_state, _max_level) \
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(_power_state) |= ((_max_level) & SCMI_PWR_STATE_MAX_PWR_LVL_MASK)\
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<< SCMI_PWR_STATE_MAX_PWR_LVL_SHIFT
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#define SCMI_GET_PWR_STATE_MAX_PWR_LVL(_power_state) \
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(((_power_state) >> SCMI_PWR_STATE_MAX_PWR_LVL_SHIFT) \
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& SCMI_PWR_STATE_MAX_PWR_LVL_MASK)
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#define SCMI_PWR_STATE_LVL_WIDTH 4
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#define SCMI_PWR_STATE_LVL_MASK \
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((1 << SCMI_PWR_STATE_LVL_WIDTH) - 1)
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#define SCMI_SET_PWR_STATE_LVL(_power_state, _level, _level_state) \
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(_power_state) |= ((_level_state) & SCMI_PWR_STATE_LVL_MASK) \
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<< (SCMI_PWR_STATE_LVL_WIDTH * (_level))
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#define SCMI_GET_PWR_STATE_LVL(_power_state, _level) \
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(((_power_state) >> (SCMI_PWR_STATE_LVL_WIDTH * (_level))) & \
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SCMI_PWR_STATE_LVL_MASK)
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/*
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* The SCMI power state enumeration for a power domain level
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*/
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typedef enum {
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scmi_power_state_off = 0,
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scmi_power_state_on = 1,
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scmi_power_state_sleep = 2,
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} scmi_power_state_t;
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/*
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* The global handle for invoking the SCMI driver APIs after the driver
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* has been initialized.
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*/
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static void *sq_scmi_handle;
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/* The SCMI channel global object */
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static scmi_channel_t channel;
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/*
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* Helper function to turn off a CPU power domain and
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* its parent power domains if applicable.
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*/
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void sq_scmi_off(const struct psci_power_state *target_state)
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{
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int lvl = 0, ret;
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uint32_t scmi_pwr_state = 0;
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/* At-least the CPU level should be specified to be OFF */
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assert(target_state->pwr_domain_state[SQ_PWR_LVL0] ==
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SQ_LOCAL_STATE_OFF);
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for (; lvl <= PLAT_MAX_PWR_LVL; lvl++) {
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if (target_state->pwr_domain_state[lvl] == SQ_LOCAL_STATE_RUN)
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break;
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assert(target_state->pwr_domain_state[lvl] ==
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SQ_LOCAL_STATE_OFF);
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SCMI_SET_PWR_STATE_LVL(scmi_pwr_state, lvl,
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scmi_power_state_off);
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}
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SCMI_SET_PWR_STATE_MAX_PWR_LVL(scmi_pwr_state, lvl - 1);
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ret = scmi_pwr_state_set(sq_scmi_handle,
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sq_core_pos_to_scmi_dmn_id_map[plat_my_core_pos()],
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scmi_pwr_state);
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if (ret != SCMI_E_QUEUED && ret != SCMI_E_SUCCESS) {
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ERROR("SCMI set power state command return 0x%x unexpected\n",
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ret);
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panic();
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}
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}
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/*
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* Helper function to turn ON a CPU power domain and
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*its parent power domains if applicable.
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*/
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void sq_scmi_on(u_register_t mpidr)
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{
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int lvl = 0, ret, core_pos;
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uint32_t scmi_pwr_state = 0;
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for (; lvl <= PLAT_MAX_PWR_LVL; lvl++)
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SCMI_SET_PWR_STATE_LVL(scmi_pwr_state, lvl,
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scmi_power_state_on);
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SCMI_SET_PWR_STATE_MAX_PWR_LVL(scmi_pwr_state, lvl - 1);
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core_pos = plat_core_pos_by_mpidr(mpidr);
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assert(core_pos >= 0 && core_pos < PLATFORM_CORE_COUNT);
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ret = scmi_pwr_state_set(sq_scmi_handle,
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sq_core_pos_to_scmi_dmn_id_map[core_pos],
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scmi_pwr_state);
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if (ret != SCMI_E_QUEUED && ret != SCMI_E_SUCCESS) {
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ERROR("SCMI set power state command return 0x%x unexpected\n",
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ret);
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panic();
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}
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}
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void __dead2 sq_scmi_system_off(int state)
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{
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int ret;
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/*
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* Disable GIC CPU interface to prevent pending interrupt from waking
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* up the AP from WFI.
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*/
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sq_gic_cpuif_disable();
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/*
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* Issue SCMI command. First issue a graceful
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* request and if that fails force the request.
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*/
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ret = scmi_sys_pwr_state_set(sq_scmi_handle,
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SCMI_SYS_PWR_FORCEFUL_REQ,
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state);
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if (ret != SCMI_E_SUCCESS) {
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ERROR("SCMI system power state set 0x%x returns unexpected 0x%x\n",
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state, ret);
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panic();
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}
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wfi();
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ERROR("SCMI set power state: operation not handled.\n");
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panic();
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}
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/*
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* Helper function to reset the system via SCMI.
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*/
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void __dead2 sq_scmi_sys_reboot(void)
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{
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sq_scmi_system_off(SCMI_SYS_PWR_COLD_RESET);
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}
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static int scmi_ap_core_init(scmi_channel_t *ch)
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{
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#if PROGRAMMABLE_RESET_ADDRESS
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uint32_t version;
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int ret;
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ret = scmi_proto_version(ch, SCMI_AP_CORE_PROTO_ID, &version);
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if (ret != SCMI_E_SUCCESS) {
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WARN("SCMI AP core protocol version message failed\n");
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return -1;
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}
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if (!is_scmi_version_compatible(SCMI_AP_CORE_PROTO_VER, version)) {
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WARN("SCMI AP core protocol version 0x%x incompatible with driver version 0x%x\n",
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version, SCMI_AP_CORE_PROTO_VER);
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return -1;
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}
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INFO("SCMI AP core protocol version 0x%x detected\n", version);
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#endif
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return 0;
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}
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void __init plat_sq_pwrc_setup(void)
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{
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channel.info = &sq_scmi_plat_info;
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channel.lock = SQ_SCMI_LOCK_GET_INSTANCE;
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sq_scmi_handle = scmi_init(&channel);
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if (sq_scmi_handle == NULL) {
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ERROR("SCMI Initialization failed\n");
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panic();
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}
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if (scmi_ap_core_init(&channel) < 0) {
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ERROR("SCMI AP core protocol initialization failed\n");
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panic();
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}
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}
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uint32_t sq_scmi_get_draminfo(struct draminfo *info)
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{
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scmi_get_draminfo(sq_scmi_handle, info);
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return 0;
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}
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@ -0,0 +1,21 @@
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/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <sq_common.h>
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#include "sq_scpi.h"
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/*
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* Helper function to get dram information from SCP.
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*/
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uint32_t sq_scp_get_draminfo(struct draminfo *info)
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{
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#if SQ_USE_SCMI_DRIVER
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sq_scmi_get_draminfo(info);
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#else
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scpi_get_draminfo(info);
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#endif
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return 0;
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}
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@ -78,5 +78,6 @@ extern void scpi_set_sq_power_state(unsigned int mpidr,
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scpi_power_state_t cluster_state,
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scpi_power_state_t css_state);
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uint32_t scpi_sys_power_state(scpi_system_state_t system_state);
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uint32_t scpi_get_draminfo(struct draminfo *info);
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#endif /* SQ_SCPI_H */
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@ -16,6 +16,16 @@
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#define PLATFORM_CORE_COUNT (PLAT_CLUSTER_COUNT * \
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PLAT_MAX_CORES_PER_CLUSTER)
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/* Macros to read the SQ power domain state */
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#define SQ_PWR_LVL0 MPIDR_AFFLVL0
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#define SQ_PWR_LVL1 MPIDR_AFFLVL1
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#define SQ_PWR_LVL2 MPIDR_AFFLVL2
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#define SQ_CORE_PWR_STATE(state) (state)->pwr_domain_state[SQ_PWR_LVL0]
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#define SQ_CLUSTER_PWR_STATE(state) (state)->pwr_domain_state[SQ_PWR_LVL1]
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#define SQ_SYSTEM_PWR_STATE(state) ((PLAT_MAX_PWR_LVL > SQ_PWR_LVL1) ?\
|
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(state)->pwr_domain_state[SQ_PWR_LVL2] : 0)
|
||||
|
||||
#define PLAT_MAX_PWR_LVL U(1)
|
||||
#define PLAT_MAX_RET_STATE U(1)
|
||||
#define PLAT_MAX_OFF_STATE U(2)
|
||||
|
|
@ -70,6 +80,7 @@
|
|||
#define DRAMINFO_BASE 0x2E00FFC0
|
||||
|
||||
#define PLAT_SQ_MHU_BASE 0x45000000
|
||||
#define PLAT_MHUV2_BASE 0xFFFFFFFF /* MHUV2 is not supported */
|
||||
|
||||
#define PLAT_SQ_SCP_COM_SHARED_MEM_BASE 0x45400000
|
||||
#define SCPI_CMD_GET_DRAMINFO 0x1
|
||||
|
|
|
|||
|
|
@ -9,6 +9,7 @@
|
|||
|
||||
#include <stdint.h>
|
||||
|
||||
#include <lib/psci/psci.h>
|
||||
#include <lib/xlat_tables/xlat_tables_v2.h>
|
||||
|
||||
struct draminfo {
|
||||
|
|
@ -22,7 +23,7 @@ struct draminfo {
|
|||
uint64_t size3;
|
||||
};
|
||||
|
||||
uint32_t scpi_get_draminfo(struct draminfo *info);
|
||||
uint32_t sq_scp_get_draminfo(struct draminfo *info);
|
||||
|
||||
void plat_sq_pwrc_setup(void);
|
||||
|
||||
|
|
@ -41,4 +42,12 @@ void sq_gic_pcpu_init(void);
|
|||
void sq_mmap_setup(uintptr_t total_base, size_t total_size,
|
||||
const struct mmap_region *mmap);
|
||||
|
||||
/* SCMI API for power management by SCP */
|
||||
void sq_scmi_off(const struct psci_power_state *target_state);
|
||||
void sq_scmi_on(u_register_t mpidr);
|
||||
void __dead2 sq_scmi_sys_reboot(void);
|
||||
void __dead2 sq_scmi_system_off(int state);
|
||||
/* SCMI API for vendor specific protocol */
|
||||
uint32_t sq_scmi_get_draminfo(struct draminfo *info);
|
||||
|
||||
#endif /* SQ_COMMON_H */
|
||||
|
|
|
|||
|
|
@ -10,9 +10,10 @@ override PROGRAMMABLE_RESET_ADDRESS := 1
|
|||
override USE_COHERENT_MEM := 1
|
||||
override SEPARATE_CODE_AND_RODATA := 1
|
||||
override ENABLE_SVE_FOR_NS := 0
|
||||
|
||||
# Enable workarounds for selected Cortex-A53 erratas.
|
||||
ERRATA_A53_855873 := 1
|
||||
# Enable SCMI support
|
||||
SQ_USE_SCMI_DRIVER ?= 0
|
||||
|
||||
# Libraries
|
||||
include lib/xlat_tables_v2/xlat_tables.mk
|
||||
|
|
@ -20,7 +21,9 @@ include lib/xlat_tables_v2/xlat_tables.mk
|
|||
PLAT_PATH := plat/socionext/synquacer
|
||||
PLAT_INCLUDES := -I$(PLAT_PATH)/include \
|
||||
-I$(PLAT_PATH)/drivers/scpi \
|
||||
-I$(PLAT_PATH)/drivers/mhu
|
||||
-I$(PLAT_PATH)/drivers/mhu \
|
||||
-Idrivers/arm/css/scmi \
|
||||
-Idrivers/arm/css/scmi/vendor
|
||||
|
||||
PLAT_BL_COMMON_SOURCES += $(PLAT_PATH)/sq_helpers.S \
|
||||
drivers/arm/pl011/aarch64/pl011_console.S \
|
||||
|
|
@ -40,12 +43,27 @@ BL31_SOURCES += drivers/arm/ccn/ccn.c \
|
|||
$(PLAT_PATH)/sq_topology.c \
|
||||
$(PLAT_PATH)/sq_psci.c \
|
||||
$(PLAT_PATH)/sq_gicv3.c \
|
||||
$(PLAT_PATH)/sq_xlat_setup.c \
|
||||
$(PLAT_PATH)/drivers/scpi/sq_scpi.c \
|
||||
$(PLAT_PATH)/sq_xlat_setup.c \
|
||||
$(PLAT_PATH)/drivers/scp/sq_scp.c
|
||||
|
||||
ifeq (${SQ_USE_SCMI_DRIVER},0)
|
||||
BL31_SOURCES += $(PLAT_PATH)/drivers/scpi/sq_scpi.c \
|
||||
$(PLAT_PATH)/drivers/mhu/sq_mhu.c
|
||||
else
|
||||
BL31_SOURCES += $(PLAT_PATH)/drivers/scp/sq_scmi.c \
|
||||
drivers/arm/css/scmi/scmi_common.c \
|
||||
drivers/arm/css/scmi/scmi_pwr_dmn_proto.c \
|
||||
drivers/arm/css/scmi/scmi_sys_pwr_proto.c \
|
||||
drivers/arm/css/scmi/vendor/scmi_sq.c \
|
||||
drivers/arm/css/mhu/css_mhu_doorbell.c
|
||||
endif
|
||||
|
||||
ifeq (${ENABLE_SPM},1)
|
||||
$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT))
|
||||
|
||||
BL31_SOURCES += $(PLAT_PATH)/sq_spm.c
|
||||
endif
|
||||
|
||||
ifeq (${SQ_USE_SCMI_DRIVER},1)
|
||||
$(eval $(call add_define,SQ_USE_SCMI_DRIVER))
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -14,7 +14,6 @@
|
|||
#include <common/debug.h>
|
||||
#include <drivers/arm/pl011.h>
|
||||
#include <lib/mmio.h>
|
||||
|
||||
#include <sq_common.h>
|
||||
|
||||
static console_pl011_t console;
|
||||
|
|
@ -83,7 +82,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
|
|||
#ifdef SPD_opteed
|
||||
struct draminfo di = {0};
|
||||
|
||||
scpi_get_draminfo(&di);
|
||||
sq_scp_get_draminfo(&di);
|
||||
|
||||
/*
|
||||
* Check if OP-TEE has been loaded in Secure RAM allocated
|
||||
|
|
@ -154,7 +153,7 @@ void bl31_plat_runtime_setup(void)
|
|||
{
|
||||
struct draminfo *di = (struct draminfo *)(unsigned long)DRAMINFO_BASE;
|
||||
|
||||
scpi_get_draminfo(di);
|
||||
sq_scp_get_draminfo(di);
|
||||
}
|
||||
|
||||
void bl31_plat_arch_setup(void)
|
||||
|
|
|
|||
|
|
@ -19,26 +19,20 @@
|
|||
#include <sq_common.h>
|
||||
#include "sq_scpi.h"
|
||||
|
||||
/* Macros to read the SQ power domain state */
|
||||
#define SQ_PWR_LVL0 MPIDR_AFFLVL0
|
||||
#define SQ_PWR_LVL1 MPIDR_AFFLVL1
|
||||
#define SQ_PWR_LVL2 MPIDR_AFFLVL2
|
||||
|
||||
#define SQ_CORE_PWR_STATE(state) (state)->pwr_domain_state[SQ_PWR_LVL0]
|
||||
#define SQ_CLUSTER_PWR_STATE(state) (state)->pwr_domain_state[SQ_PWR_LVL1]
|
||||
#define SQ_SYSTEM_PWR_STATE(state) ((PLAT_MAX_PWR_LVL > SQ_PWR_LVL1) ?\
|
||||
(state)->pwr_domain_state[SQ_PWR_LVL2] : 0)
|
||||
|
||||
uintptr_t sq_sec_entrypoint;
|
||||
|
||||
int sq_pwr_domain_on(u_register_t mpidr)
|
||||
{
|
||||
#if SQ_USE_SCMI_DRIVER
|
||||
sq_scmi_on(mpidr);
|
||||
#else
|
||||
/*
|
||||
* SCP takes care of powering up parent power domains so we
|
||||
* only need to care about level 0
|
||||
*/
|
||||
scpi_set_sq_power_state(mpidr, scpi_power_on, scpi_power_on,
|
||||
scpi_power_on);
|
||||
#endif
|
||||
|
||||
return PSCI_E_SUCCESS;
|
||||
}
|
||||
|
|
@ -70,6 +64,7 @@ void sq_pwr_domain_on_finish(const psci_power_state_t *target_state)
|
|||
sq_gic_cpuif_enable();
|
||||
}
|
||||
|
||||
#if !SQ_USE_SCMI_DRIVER
|
||||
static void sq_power_down_common(const psci_power_state_t *target_state)
|
||||
{
|
||||
uint32_t cluster_state = scpi_power_on;
|
||||
|
|
@ -97,10 +92,15 @@ static void sq_power_down_common(const psci_power_state_t *target_state)
|
|||
cluster_state,
|
||||
system_state);
|
||||
}
|
||||
#endif
|
||||
|
||||
void sq_pwr_domain_off(const psci_power_state_t *target_state)
|
||||
{
|
||||
#if SQ_USE_SCMI_DRIVER
|
||||
sq_scmi_off(target_state);
|
||||
#else
|
||||
sq_power_down_common(target_state);
|
||||
#endif
|
||||
}
|
||||
|
||||
void __dead2 sq_system_off(void)
|
||||
|
|
@ -135,6 +135,9 @@ void __dead2 sq_system_off(void)
|
|||
|
||||
void __dead2 sq_system_reset(void)
|
||||
{
|
||||
#if SQ_USE_SCMI_DRIVER
|
||||
sq_scmi_sys_reboot();
|
||||
#else
|
||||
uint32_t response;
|
||||
|
||||
/* Send the system reset request to the SCP */
|
||||
|
|
@ -147,6 +150,7 @@ void __dead2 sq_system_reset(void)
|
|||
wfi();
|
||||
ERROR("SQ System Reset: operation not handled.\n");
|
||||
panic();
|
||||
#endif
|
||||
}
|
||||
|
||||
void sq_cpu_standby(plat_local_state_t cpu_state)
|
||||
|
|
|
|||
Loading…
Reference in New Issue