Re-design bakery lock memory allocation and algorithm
This patch unifies the bakery lock api's across coherent and normal memory implementation of locks by using same data type `bakery_lock_t` and similar arguments to functions. A separate section `bakery_lock` has been created and used to allocate memory for bakery locks using `DEFINE_BAKERY_LOCK`. When locks are allocated in normal memory, each lock for a core has to spread across multiple cache lines. By using the total size allocated in a separate cache line for a single core at compile time, the memory for other core locks is allocated at link time by multiplying the single core locks size with (PLATFORM_CORE_COUNT - 1). The normal memory lock algorithm now uses lock address instead of the `id` in the per_cpu_data. For locks allocated in coherent memory, it moves locks from tzfw_coherent_memory to bakery_lock section. The bakery locks are allocated as part of bss or in coherent memory depending on usage of coherent memory. Both these regions are initialised to zero as part of run_time_init before locks are used. Hence, bakery_lock_init() is made an empty function as the lock memory is already initialised to zero. The above design lead to the removal of psci bakery locks from non_cpu_power_pd_node to psci_locks. NOTE: THE BAKERY LOCK API WHEN USE_COHERENT_MEM IS NOT SET HAS CHANGED. THIS IS A BREAKING CHANGE FOR ALL PLATFORM PORTS THAT ALLOCATE BAKERY LOCKS IN NORMAL MEMORY. Change-Id: Ic3751c0066b8032dcbf9d88f1d4dc73d15f61d8b
This commit is contained in:
Andrew Thoelke
Vikram Kanigiri
parent
604d5da6f2
commit
ee7b35c4e1
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@ -101,10 +101,31 @@ SECTIONS
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* The .bss section gets initialised to 0 at runtime.
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* Its base address must be 16-byte aligned.
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*/
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.bss : ALIGN(16) {
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.bss (NOLOAD) : ALIGN(16) {
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__BSS_START__ = .;
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*(.bss*)
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*(COMMON)
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#if !USE_COHERENT_MEM
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/*
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* Bakery locks are stored in normal .bss memory
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*
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* Each lock's data is spread across multiple cache lines, one per CPU,
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* but multiple locks can share the same cache line.
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* The compiler will allocate enough memory for one CPU's bakery locks,
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* the remaining cache lines are allocated by the linker script
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*/
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. = ALIGN(CACHE_WRITEBACK_GRANULE);
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__BAKERY_LOCK_START__ = .;
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*(bakery_lock)
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. = ALIGN(CACHE_WRITEBACK_GRANULE);
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__PERCPU_BAKERY_LOCK_SIZE__ = . - __BAKERY_LOCK_START__;
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. = . + (__PERCPU_BAKERY_LOCK_SIZE__ * (PLATFORM_CORE_COUNT - 1));
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__BAKERY_LOCK_END__ = .;
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#ifdef PLAT_PERCPU_BAKERY_LOCK_SIZE
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ASSERT(__PERCPU_BAKERY_LOCK_SIZE__ == PLAT_PERCPU_BAKERY_LOCK_SIZE,
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"PLAT_PERCPU_BAKERY_LOCK_SIZE does not match bakery lock requirements");
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#endif
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#endif
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__BSS_END__ = .;
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} >RAM
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@ -126,6 +147,12 @@ SECTIONS
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*/
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coherent_ram (NOLOAD) : ALIGN(4096) {
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__COHERENT_RAM_START__ = .;
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/*
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* Bakery locks are stored in coherent memory
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*
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* Each lock's data is contiguous and fully allocated by the compiler
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*/
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*(bakery_lock)
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*(tzfw_coherent_mem)
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__COHERENT_RAM_END_UNALIGNED__ = .;
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/*
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@ -1523,38 +1523,52 @@ approach described above.
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The below sections analyze the data structures allocated in the coherent memory
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region and the changes required to allocate them in normal memory.
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### PSCI Affinity map nodes
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### Coherent memory usage in PSCI implementation
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The `psci_aff_map` data structure stores the hierarchial node information for
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each affinity level in the system including the PSCI states associated with them.
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By default, this data structure is allocated in the coherent memory region in
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the Trusted Firmware because it can be accessed by multiple CPUs, either with
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their caches enabled or disabled.
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The `psci_non_cpu_pd_nodes` data structure stores the platform's power domain
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tree information for state management of power domains. By default, this data
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structure is allocated in the coherent memory region in the Trusted Firmware
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because it can be accessed by multple CPUs, either with caches enabled or
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disabled.
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typedef struct aff_map_node {
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unsigned long mpidr;
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unsigned char ref_count;
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unsigned char state;
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unsigned char level;
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#if USE_COHERENT_MEM
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bakery_lock_t lock;
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#else
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unsigned char aff_map_index;
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#endif
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} aff_map_node_t;
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typedef struct non_cpu_pwr_domain_node {
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/*
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* Index of the first CPU power domain node level 0 which has this node
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* as its parent.
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*/
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unsigned int cpu_start_idx;
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/*
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* Number of CPU power domains which are siblings of the domain indexed
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* by 'cpu_start_idx' i.e. all the domains in the range 'cpu_start_idx
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* -> cpu_start_idx + ncpus' have this node as their parent.
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*/
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unsigned int ncpus;
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/*
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* Index of the parent power domain node.
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* TODO: Figure out whether to whether using pointer is more efficient.
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*/
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unsigned int parent_node;
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plat_local_state_t local_state;
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unsigned char level;
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/* For indexing the psci_lock array*/
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unsigned char lock_index;
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} non_cpu_pd_node_t;
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In order to move this data structure to normal memory, the use of each of its
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fields must be analyzed. Fields like `mpidr` and `level` are only written once
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during cold boot. Hence removing them from coherent memory involves only doing
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a clean and invalidate of the cache lines after these fields are written.
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fields must be analyzed. Fields like `cpu_start_idx`, `ncpus`, `parent_node`
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`level` and `lock_index` are only written once during cold boot. Hence removing
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them from coherent memory involves only doing a clean and invalidate of the
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cache lines after these fields are written.
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The fields `state` and `ref_count` can be concurrently accessed by multiple
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CPUs in different cache states. A Lamport's Bakery lock is used to ensure mutual
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exlusion to these fields. As a result, it is possible to move these fields out
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of coherent memory by performing software cache maintenance on them. The field
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`lock` is the bakery lock data structure when `USE_COHERENT_MEM` is enabled.
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The `aff_map_index` is used to identify the bakery lock when `USE_COHERENT_MEM`
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is disabled.
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The field `local_state` can be concurrently accessed by multiple CPUs in
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different cache states. A Lamport's Bakery lock `psci_locks` is used to ensure
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mutual exlusion to this field and a clean and invalidate is needed after it
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is written.
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### Bakery lock data
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@ -1563,9 +1577,13 @@ and is accessed by multiple CPUs with mismatched attributes. `bakery_lock_t` is
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defined as follows:
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typedef struct bakery_lock {
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int owner;
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volatile char entering[BAKERY_LOCK_MAX_CPUS];
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volatile unsigned number[BAKERY_LOCK_MAX_CPUS];
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/*
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* The lock_data is a bit-field of 2 members:
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* Bit[0] : choosing. This field is set when the CPU is
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* choosing its bakery number.
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* Bits[1 - 15] : number. This is the bakery number allocated.
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*/
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volatile uint16_t lock_data[BAKERY_LOCK_MAX_CPUS];
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} bakery_lock_t;
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It is a characteristic of Lamport's Bakery algorithm that the volatile per-CPU
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@ -1589,17 +1607,14 @@ the update made by CPU0 as well.
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To use bakery locks when `USE_COHERENT_MEM` is disabled, the lock data structure
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has been redesigned. The changes utilise the characteristic of Lamport's Bakery
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algorithm mentioned earlier. The per-CPU fields of the new lock structure are
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aligned such that they are allocated on separate cache lines. The per-CPU data
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framework in Trusted Firmware is used to achieve this. This enables software to
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algorithm mentioned earlier. The bakery_lock structure only allocates the memory
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for a single CPU. The macro `DEFINE_BAKERY_LOCK` allocates all the bakery locks
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needed for a CPU into a section `bakery_lock`. The linker allocates the memory
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for other cores by using the total size allocated for the bakery_lock section
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and multiplying it with (PLATFORM_CORE_COUNT - 1). This enables software to
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perform software cache maintenance on the lock data structure without running
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into coherency issues associated with mismatched attributes.
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The per-CPU data framework enables consolidation of data structures on the
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fewest cache lines possible. This saves memory as compared to the scenario where
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each data structure is separately aligned to the cache line boundary to achieve
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the same effect.
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The bakery lock data structure `bakery_info_t` is defined for use when
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`USE_COHERENT_MEM` is disabled as follows:
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@ -1615,12 +1630,10 @@ The bakery lock data structure `bakery_info_t` is defined for use when
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The `bakery_info_t` represents a single per-CPU field of one lock and
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the combination of corresponding `bakery_info_t` structures for all CPUs in the
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system represents the complete bakery lock. It is embedded in the per-CPU
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data framework `cpu_data` as shown below:
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system represents the complete bakery lock. The view in memory for a system
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with n bakery locks are:
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CPU0 cpu_data
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------------------
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| .... |
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bakery_lock section start
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|----------------|
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| `bakery_info_t`| <-- Lock_0 per-CPU field
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| Lock_0 | for CPU0
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@ -1633,12 +1646,11 @@ data framework `cpu_data` as shown below:
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| `bakery_info_t`| <-- Lock_N per-CPU field
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| Lock_N | for CPU0
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------------------
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CPU1 cpu_data
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| XXXXX |
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| Padding to |
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| next Cache WB | <--- Calculate PERCPU_BAKERY_LOCK_SIZE, allocate
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| Granule | continuous memory for remaining CPUs.
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------------------
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| .... |
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|----------------|
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| `bakery_info_t`| <-- Lock_0 per-CPU field
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| Lock_0 | for CPU1
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|----------------|
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@ -1650,14 +1662,20 @@ data framework `cpu_data` as shown below:
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| `bakery_info_t`| <-- Lock_N per-CPU field
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| Lock_N | for CPU1
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------------------
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| XXXXX |
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| Padding to |
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| next Cache WB |
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| Granule |
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------------------
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Consider a system of 2 CPUs with 'N' bakery locks as shown above. For an
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Consider a system of 2 CPUs with 'N' bakery locks as shown above. For an
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operation on Lock_N, the corresponding `bakery_info_t` in both CPU0 and CPU1
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`cpu_data` need to be fetched and appropriate cache operations need to be
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performed for each access.
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`bakery_lock` section need to be fetched and appropriate cache operations need
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to be performed for each access.
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On ARM Platforms, bakery locks are used in psci (`psci_locks`) and power controller
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driver (`arm_lock`).
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For multiple bakery locks, an array of `bakery_info_t` is declared in `cpu_data`
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and each lock is given an `id` to identify it in the array.
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### Non Functional Impact of removing coherent memory
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@ -1680,10 +1698,9 @@ Juno ARM development platform.
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As mentioned earlier, almost a page of memory can be saved by disabling
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`USE_COHERENT_MEM`. Each platform needs to consider these trade-offs to decide
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whether coherent memory should be used. If a platform disables
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`USE_COHERENT_MEM` and needs to use bakery locks in the porting layer, it should
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reserve memory in `cpu_data` by defining the macro `PLAT_PCPU_DATA_SIZE` (see
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the [Porting Guide]). Refer to the reference platform code for examples.
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`USE_COHERENT_MEM` and needs to use bakery locks in the porting layer, it can
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optionally define macro `PLAT_PERCPU_BAKERY_LOCK_SIZE` (see the [Porting
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Guide]). Refer to the reference platform code for examples.
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12. Code Structure
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-------------------
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@ -76,21 +76,24 @@ mapped page tables, and enable both the instruction and data caches for each BL
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stage. In ARM standard platforms, each BL stage configures the MMU in
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the platform-specific architecture setup function, `blX_plat_arch_setup()`.
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If the build option `USE_COHERENT_MEM` is enabled, each platform must allocate a
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If the build option `USE_COHERENT_MEM` is enabled, each platform can allocate a
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block of identity mapped secure memory with Device-nGnRE attributes aligned to
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page boundary (4K) for each BL stage. This memory is identified by the section
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name `tzfw_coherent_mem` so that its possible for the firmware to place
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variables in it using the following C code directive:
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page boundary (4K) for each BL stage. All sections which allocate coherent
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memory are grouped under `coherent_ram`. For ex: Bakery locks are placed in a
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section identified by name `bakery_lock` inside `coherent_ram` so that its
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possible for the firmware to place variables in it using the following C code
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directive:
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__attribute__ ((section("tzfw_coherent_mem")))
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__attribute__ ((section("bakery_lock")))
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Or alternatively the following assembler code directive:
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.section tzfw_coherent_mem
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.section bakery_lock
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The `tzfw_coherent_mem` section is used to allocate any data structures that are
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accessed both when a CPU is executing with its MMU and caches enabled, and when
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it's running with its MMU and caches disabled. Examples are given below.
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The `coherent_ram` section is a sum of all sections like `bakery_lock` which are
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used to allocate any data structures that are accessed both when a CPU is
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executing with its MMU and caches enabled, and when it's running with its MMU
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and caches disabled. Examples are given below.
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The following variables, functions and constants must be defined by the platform
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for the firmware to work correctly.
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@ -1150,6 +1153,12 @@ of the system counter, which is retrieved from the first entry in the frequency
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modes table.
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* **#define : PLAT_PERCPU_BAKERY_LOCK_SIZE** [optional]
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It is used if the bakery locks are using normal memory. It defines the memory
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(in bytes) to be allocated for the bakery locks and needs to be a multiple of
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cache line size.
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3.3 Power State Coordination Interface (in BL3-1)
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------------------------------------------------
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@ -251,9 +251,6 @@ typedef struct psci_cpu_data {
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/* The local power state of this CPU */
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plat_local_state_t local_state;
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#if !USE_COHERENT_MEM
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bakery_info_t pcpu_bakery_info[PSCI_NUM_NON_CPU_PWR_DOMAINS];
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#endif
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} psci_cpu_data_t;
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/*******************************************************************************
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@ -56,6 +56,11 @@
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* External bakery lock interface.
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****************************************************************************/
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#if USE_COHERENT_MEM
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/*
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* Bakery locks are stored in coherent memory
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*
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* Each lock's data is contiguous and fully allocated by the compiler
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*/
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typedef struct bakery_lock {
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/*
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@ -67,12 +72,15 @@ typedef struct bakery_lock {
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volatile uint16_t lock_data[BAKERY_LOCK_MAX_CPUS];
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} bakery_lock_t;
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void bakery_lock_init(bakery_lock_t *bakery);
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void bakery_lock_get(bakery_lock_t *bakery);
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void bakery_lock_release(bakery_lock_t *bakery);
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int bakery_lock_try(bakery_lock_t *bakery);
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#else
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/*
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* Bakery locks are stored in normal .bss memory
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*
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* Each lock's data is spread across multiple cache lines, one per CPU,
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* but multiple locks can share the same cache line.
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* The compiler will allocate enough memory for one CPU's bakery locks,
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* the remaining cache lines are allocated by the linker script
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*/
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typedef struct bakery_info {
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/*
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@ -84,9 +92,19 @@ typedef struct bakery_info {
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volatile uint16_t lock_data;
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} bakery_info_t;
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void bakery_lock_get(unsigned int id, unsigned int offset);
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void bakery_lock_release(unsigned int id, unsigned int offset);
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typedef bakery_info_t bakery_lock_t;
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#endif /* __USE_COHERENT_MEM__ */
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inline void bakery_lock_init(bakery_lock_t *bakery) {}
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void bakery_lock_get(bakery_lock_t *bakery);
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void bakery_lock_release(bakery_lock_t *bakery);
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#define DEFINE_BAKERY_LOCK(_name) bakery_lock_t _name \
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__attribute__ ((section("bakery_lock")))
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#define DECLARE_BAKERY_LOCK(_name) extern bakery_lock_t _name
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#endif /* __ASSEMBLY__ */
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#endif /* __BAKERY_LOCK_H__ */
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@ -63,16 +63,6 @@
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assert(entry < BAKERY_LOCK_MAX_CPUS); \
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} while (0)
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/* Initialize Bakery Lock to reset all ticket values */
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void bakery_lock_init(bakery_lock_t *bakery)
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{
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assert(bakery);
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/* All ticket values need to be 0 */
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memset(bakery, 0, sizeof(*bakery));
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}
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/* Obtain a ticket for a given CPU */
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static unsigned int bakery_get_ticket(bakery_lock_t *bakery, unsigned int me)
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{
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@ -56,12 +56,29 @@
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* accesses regardless of status of address translation.
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*/
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/* This macro assumes that the bakery_info array is located at the offset specified */
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#define get_my_bakery_info(offset, id) \
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(((bakery_info_t *) (((uint8_t *)_cpu_data()) + offset)) + id)
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#ifdef PLAT_PERCPU_BAKERY_LOCK_SIZE
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/*
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* Verify that the platform defined value for the per-cpu space for bakery locks is
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* a multiple of the cache line size, to prevent multiple CPUs writing to the same
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* bakery lock cache line
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*
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* Using this value, if provided, rather than the linker generated value results in
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* more efficient code
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*/
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CASSERT((PLAT_PERCPU_BAKERY_LOCK_SIZE & (CACHE_WRITEBACK_GRANULE - 1)) == 0, \
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PLAT_PERCPU_BAKERY_LOCK_SIZE_not_cacheline_multiple);
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#define PERCPU_BAKERY_LOCK_SIZE (PLAT_PERCPU_BAKERY_LOCK_SIZE)
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#else
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/*
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* Use the linker defined symbol which has evaluated the size reqiurement.
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* This is not as efficient as using a platform defined constant
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*/
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extern void *__PERCPU_BAKERY_LOCK_SIZE__;
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#define PERCPU_BAKERY_LOCK_SIZE ((uintptr_t)&__PERCPU_BAKERY_LOCK_SIZE__)
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#endif
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#define get_bakery_info_by_index(offset, id, ix) \
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(((bakery_info_t *) (((uint8_t *)_cpu_data_by_index(ix)) + offset)) + id)
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||||
#define get_bakery_info(cpu_ix, lock) \
|
||||
(bakery_info_t *)((uintptr_t)lock + cpu_ix * PERCPU_BAKERY_LOCK_SIZE)
|
||||
|
||||
#define write_cache_op(addr, cached) \
|
||||
do { \
|
||||
|
|
@ -73,7 +90,7 @@
|
|||
#define read_cache_op(addr, cached) if (cached) \
|
||||
dccivac((uint64_t)addr)
|
||||
|
||||
static unsigned int bakery_get_ticket(int id, unsigned int offset,
|
||||
static unsigned int bakery_get_ticket(bakery_lock_t *lock,
|
||||
unsigned int me, int is_cached)
|
||||
{
|
||||
unsigned int my_ticket, their_ticket;
|
||||
|
|
@ -84,7 +101,7 @@ static unsigned int bakery_get_ticket(int id, unsigned int offset,
|
|||
* Obtain a reference to the bakery information for this cpu and ensure
|
||||
* it is not NULL.
|
||||
*/
|
||||
my_bakery_info = get_my_bakery_info(offset, id);
|
||||
my_bakery_info = get_bakery_info(me, lock);
|
||||
assert(my_bakery_info);
|
||||
|
||||
/*
|
||||
|
|
@ -115,7 +132,7 @@ static unsigned int bakery_get_ticket(int id, unsigned int offset,
|
|||
* Get a reference to the other contender's bakery info and
|
||||
* ensure that a stale copy is not read.
|
||||
*/
|
||||
their_bakery_info = get_bakery_info_by_index(offset, id, they);
|
||||
their_bakery_info = get_bakery_info(they, lock);
|
||||
assert(their_bakery_info);
|
||||
|
||||
read_cache_op(their_bakery_info, is_cached);
|
||||
|
|
@ -141,7 +158,7 @@ static unsigned int bakery_get_ticket(int id, unsigned int offset,
|
|||
return my_ticket;
|
||||
}
|
||||
|
||||
void bakery_lock_get(unsigned int id, unsigned int offset)
|
||||
void bakery_lock_get(bakery_lock_t *lock)
|
||||
{
|
||||
unsigned int they, me, is_cached;
|
||||
unsigned int my_ticket, my_prio, their_ticket;
|
||||
|
|
@ -153,7 +170,7 @@ void bakery_lock_get(unsigned int id, unsigned int offset)
|
|||
is_cached = read_sctlr_el3() & SCTLR_C_BIT;
|
||||
|
||||
/* Get a ticket */
|
||||
my_ticket = bakery_get_ticket(id, offset, me, is_cached);
|
||||
my_ticket = bakery_get_ticket(lock, me, is_cached);
|
||||
|
||||
/*
|
||||
* Now that we got our ticket, compute our priority value, then compare
|
||||
|
|
@ -168,7 +185,7 @@ void bakery_lock_get(unsigned int id, unsigned int offset)
|
|||
* Get a reference to the other contender's bakery info and
|
||||
* ensure that a stale copy is not read.
|
||||
*/
|
||||
their_bakery_info = get_bakery_info_by_index(offset, id, they);
|
||||
their_bakery_info = get_bakery_info(they, lock);
|
||||
assert(their_bakery_info);
|
||||
|
||||
/* Wait for the contender to get their ticket */
|
||||
|
|
@ -199,12 +216,12 @@ void bakery_lock_get(unsigned int id, unsigned int offset)
|
|||
/* Lock acquired */
|
||||
}
|
||||
|
||||
void bakery_lock_release(unsigned int id, unsigned int offset)
|
||||
void bakery_lock_release(bakery_lock_t *lock)
|
||||
{
|
||||
bakery_info_t *my_bakery_info;
|
||||
unsigned int is_cached = read_sctlr_el3() & SCTLR_C_BIT;
|
||||
|
||||
my_bakery_info = get_my_bakery_info(offset, id);
|
||||
my_bakery_info = get_bakery_info(plat_my_core_pos(), lock);
|
||||
assert(bakery_ticket_number(my_bakery_info->lock_data));
|
||||
|
||||
my_bakery_info->lock_data = 0;
|
||||
|
|
|
|||
|
|
@ -78,6 +78,8 @@ __attribute__ ((section("tzfw_coherent_mem")))
|
|||
#endif
|
||||
;
|
||||
|
||||
DEFINE_BAKERY_LOCK(psci_locks[PSCI_NUM_NON_CPU_PWR_DOMAINS]);
|
||||
|
||||
cpu_pd_node_t psci_cpu_pd_nodes[PLATFORM_CORE_COUNT];
|
||||
|
||||
/*******************************************************************************
|
||||
|
|
|
|||
|
|
@ -42,23 +42,12 @@
|
|||
* The following helper macros abstract the interface to the Bakery
|
||||
* Lock API.
|
||||
*/
|
||||
#if USE_COHERENT_MEM
|
||||
#define psci_lock_init(non_cpu_pd_node, idx) \
|
||||
bakery_lock_init(&(non_cpu_pd_node)[(idx)].lock)
|
||||
#define psci_lock_get(non_cpu_pd_node) \
|
||||
bakery_lock_get(&((non_cpu_pd_node)->lock))
|
||||
#define psci_lock_release(non_cpu_pd_node) \
|
||||
bakery_lock_release(&((non_cpu_pd_node)->lock))
|
||||
#else
|
||||
#define psci_lock_init(non_cpu_pd_node, idx) \
|
||||
((non_cpu_pd_node)[(idx)].lock_index = (idx))
|
||||
#define psci_lock_get(non_cpu_pd_node) \
|
||||
bakery_lock_get((non_cpu_pd_node)->lock_index, \
|
||||
CPU_DATA_PSCI_LOCK_OFFSET)
|
||||
bakery_lock_get(&psci_locks[(non_cpu_pd_node)->lock_index])
|
||||
#define psci_lock_release(non_cpu_pd_node) \
|
||||
bakery_lock_release((non_cpu_pd_node)->lock_index, \
|
||||
CPU_DATA_PSCI_LOCK_OFFSET)
|
||||
#endif
|
||||
bakery_lock_release(&psci_locks[(non_cpu_pd_node)->lock_index])
|
||||
|
||||
/*
|
||||
* The PSCI capability which are provided by the generic code but does not
|
||||
|
|
@ -140,12 +129,9 @@ typedef struct non_cpu_pwr_domain_node {
|
|||
plat_local_state_t local_state;
|
||||
|
||||
unsigned char level;
|
||||
#if USE_COHERENT_MEM
|
||||
bakery_lock_t lock;
|
||||
#else
|
||||
/* For indexing the bakery_info array in per CPU data */
|
||||
|
||||
/* For indexing the psci_lock array*/
|
||||
unsigned char lock_index;
|
||||
#endif
|
||||
} non_cpu_pd_node_t;
|
||||
|
||||
typedef struct cpu_pwr_domain_node {
|
||||
|
|
@ -174,6 +160,9 @@ extern non_cpu_pd_node_t psci_non_cpu_pd_nodes[PSCI_NUM_NON_CPU_PWR_DOMAINS];
|
|||
extern cpu_pd_node_t psci_cpu_pd_nodes[PLATFORM_CORE_COUNT];
|
||||
extern unsigned int psci_caps;
|
||||
|
||||
/* One bakery lock is required for each non-cpu power domain */
|
||||
DECLARE_BAKERY_LOCK(psci_locks[PSCI_NUM_NON_CPU_PWR_DOMAINS]);
|
||||
|
||||
/*******************************************************************************
|
||||
* SPD's power management hooks registered with PSCI
|
||||
******************************************************************************/
|
||||
|
|
|
|||
|
|
@ -181,12 +181,6 @@ static void populate_power_domain_tree(const unsigned char *topology)
|
|||
|
||||
/* Validate the sanity of array exported by the platform */
|
||||
assert(j == PLATFORM_CORE_COUNT);
|
||||
|
||||
#if !USE_COHERENT_MEM
|
||||
/* Flush the non CPU power domain data to memory */
|
||||
flush_dcache_range((uintptr_t) &psci_non_cpu_pd_nodes,
|
||||
sizeof(psci_non_cpu_pd_nodes));
|
||||
#endif
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
|
|
|
|||
Loading…
Reference in New Issue