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Merge changes I959d1343,I6992df1a,I687e35cb,Ia5f2ee31,Ifd0bc6aa, ... into integration 

* changes:
  docs: marvell: update mv_ddr branch
  plat: marvell: armada: a3k: rename the UART images archive
  plat: marvell: armada: a3k: allow image load to RAM address 0
  marvell: comphy: cp110: add support for USB comphy polarity invert
  marvell: comphy: cp110: add support for SATA comphy polarity invert
  marvell: comphy: cp110: implement erratum IPCE_COMPHY-1353
  drivers: marvell: mochi: Update AP incoming masters secure level
  plat: marvell: armada: add ccu window for workaround errata-id 3033912
  plat: marvell: ap806: implement workaround for errata-id FE-4265711
This commit is contained in:
Manish Pandey 2020-10-06 08:42:53 +00:00 committed by TrustedFirmware Code Review
parent f8dee97bab 1d935a1b55
commit eeb77da646
14 changed files with 247 additions and 27 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
docs/plat/marvell/armada/build.rst
View File

@ -259,7 +259,7 @@ Armada37x0 Builds require installation of 3 components
> export CROSS_CM3=/opt/arm-cross/bin/arm-linux-gnueabi
(2) DDR initialization library sources (mv_ddr) available at the following repository
(use the "mv_ddr-armada-atf-mainline" branch):
(use the "mv_ddr-armada-18.12" branch):
https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git
@ -271,6 +271,6 @@ Armada70x0 and Armada80x0 Builds require installation of an additional component
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
(1) DDR initialization library sources (mv_ddr) available at the following repository
(use the "mv_ddr-armada-atf-mainline" branch):
(use the "mv_ddr-armada-18.12" branch):
https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git

41
drivers/marvell/ccu.c
View File

@ -26,11 +26,38 @@
#define ADDRESS_MASK (0xFFFFFFF0)
#define CCU_WIN_ALIGNMENT (0x100000)
/*
* Physical address of the highest address of window bits[31:19] = 0x6FF
* Physical address of the lowest address of window bits[18:6] = 0x6E0
* Unit Id bits [5:2] = 2
* RGF Window Enable bit[0] = 1
* 0x37f9b809 - 11011111111 0011011100000 0010 0 1
*/
#define ERRATA_WA_CCU_WIN4 0x37f9b809U
/*
* Physical address of the highest address of window bits[31:19] = 0xFFF
* Physical address of the lowest address of window bits[18:6] = 0x800
* Unit Id bits [5:2] = 2
* RGF Window Enable bit[0] = 1
* 0x7ffa0009 - 111111111111 0100000000000 0010 0 1
*/
#define ERRATA_WA_CCU_WIN5 0x7ffa0009U
/*
* Physical address of the highest address of window bits[31:19] = 0x1FFF
* Physical address of the lowest address of window bits[18:6] = 0x1000
* Unit Id bits [5:2] = 2
* RGF Window Enable bit[0] = 1
* 0xfffc000d - 1111111111111 1000000000000 0011 0 1
*/
#define ERRATA_WA_CCU_WIN6 0xfffc000dU
#define IS_DRAM_TARGET(tgt) ((((tgt) == DRAM_0_TID) || \
((tgt) == DRAM_1_TID) || \
((tgt) == RAR_TID)) ? 1 : 0)
#define CCU_RGF(win) (MVEBU_CCU_BASE(MVEBU_AP0) + \
#define CCU_RGF(win) (MVEBU_CCU_BASE(MVEBU_AP0) + \
0x90 + 4 * (win))
/* For storage of CR, SCR, ALR, AHR abd GCR */
@ -376,10 +403,12 @@ void errata_wa_init(void)
* EERATA ID: RES-3033912 - Internal Address Space Init state causes
* a hang upon accesses to [0xf070_0000, 0xf07f_ffff]
* Workaround: Boot Firmware (ATF) should configure CCU_RGF_WIN(4) to
* split [0x6e_0000, 0xff_ffff] to values [0x6e_0000, 0x6f_ffff] and
* [0x80_0000, 0xff_ffff] that cause accesses to the
* segment of [0xf070_0000, 0xf07f_ffff] to act as RAZWI.
* split [0x6e_0000, 0x1ff_ffff] to values [0x6e_0000, 0x6f_ffff] and
* [0x80_0000, 0xff_ffff] and [0x100_0000, 0x1ff_ffff],that cause
* accesses to the segment of [0xf070_0000, 0xf1ff_ffff]
* to act as RAZWI.
*/
mmio_write_32(CCU_RGF(4), 0x37f9b809);
mmio_write_32(CCU_RGF(5), 0x7ffa0009);
mmio_write_32(CCU_RGF(4), ERRATA_WA_CCU_WIN4);
mmio_write_32(CCU_RGF(5), ERRATA_WA_CCU_WIN5);
mmio_write_32(CCU_RGF(6), ERRATA_WA_CCU_WIN6);
}

11
drivers/marvell/comphy/comphy-cp110.h
View File

@ -116,6 +116,9 @@
(0x1 << SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET)
#define SD_EXTERNAL_CONFIG1_REG 0x4
#define SD_EXTERNAL_CONFIG1_TX_IDLE_OFFSET 2
#define SD_EXTERNAL_CONFIG1_TX_IDLE_MASK \
(0x1 << SD_EXTERNAL_CONFIG1_TX_IDLE_OFFSET)
#define SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET 3
#define SD_EXTERNAL_CONFIG1_RESET_IN_MASK \
(0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET)
@ -352,6 +355,14 @@
#define HPIPE_CDR_LOCK_DET_EN_MASK \
(0x1 << HPIPE_CDR_LOCK_DET_EN_OFFSET)
#define HPIPE_SYNC_PATTERN_REG 0x090
#define HPIPE_SYNC_PATTERN_TXD_INV_OFFSET 10
#define HPIPE_SYNC_PATTERN_TXD_INV_MASK \
(0x1 << HPIPE_SYNC_PATTERN_TXD_INV_OFFSET)
#define HPIPE_SYNC_PATTERN_RXD_INV_OFFSET 11
#define HPIPE_SYNC_PATTERN_RXD_INV_MASK \
(0x1 << HPIPE_SYNC_PATTERN_RXD_INV_OFFSET)
#define HPIPE_INTERFACE_REG 0x94
#define HPIPE_INTERFACE_GEN_MAX_OFFSET 10
#define HPIPE_INTERFACE_GEN_MAX_MASK \

54
drivers/marvell/comphy/phy-comphy-cp110.c
View File

@ -323,12 +323,33 @@ int mvebu_cp110_comphy_is_pll_locked(uint64_t comphy_base, uint8_t comphy_index)
return ret;
}
static void mvebu_cp110_polarity_invert(uintptr_t addr, uint8_t phy_polarity_invert)
{
uint32_t mask, data;
/* Set RX / TX polarity */
data = mask = 0x0U;
if ((phy_polarity_invert & COMPHY_POLARITY_TXD_INVERT) != 0) {
data |= (1 << HPIPE_SYNC_PATTERN_TXD_INV_OFFSET);
mask |= HPIPE_SYNC_PATTERN_TXD_INV_MASK;
debug("%s: inverting TX polarity\n", __func__);
}
if ((phy_polarity_invert & COMPHY_POLARITY_RXD_INVERT) != 0) {
data |= (1 << HPIPE_SYNC_PATTERN_RXD_INV_OFFSET);
mask |= HPIPE_SYNC_PATTERN_RXD_INV_MASK;
debug("%s: inverting RX polarity\n", __func__);
}
reg_set(addr, data, mask);
}
static int mvebu_cp110_comphy_sata_power_on(uint64_t comphy_base,
uint8_t comphy_index, uint32_t comphy_mode)
{
uintptr_t hpipe_addr, sd_ip_addr, comphy_addr;
uint32_t mask, data;
uint8_t ap_nr, cp_nr;
uint8_t ap_nr, cp_nr, phy_polarity_invert;
int ret = 0;
debug_enter();
@ -338,6 +359,7 @@ static int mvebu_cp110_comphy_sata_power_on(uint64_t comphy_base,
const struct sata_params *sata_static_values =
&sata_static_values_tab[ap_nr][cp_nr][comphy_index];
phy_polarity_invert = sata_static_values->polarity_invert;
/* configure phy selector for SATA */
mvebu_cp110_comphy_set_phy_selector(comphy_base,
@ -629,6 +651,11 @@ static int mvebu_cp110_comphy_sata_power_on(uint64_t comphy_base,
reg_set(hpipe_addr + HPIPE_PWR_CTR_REG,
0x0 << HPIPE_PWR_CTR_RST_DFE_OFFSET,
HPIPE_PWR_CTR_RST_DFE_MASK);
if (phy_polarity_invert != 0)
mvebu_cp110_polarity_invert(hpipe_addr + HPIPE_SYNC_PATTERN_REG,
phy_polarity_invert);
/* SW reset for interrupt logic */
reg_set(hpipe_addr + HPIPE_PWR_CTR_REG,
0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET,
@ -898,11 +925,21 @@ static int mvebu_cp110_comphy_xfi_power_on(uint64_t comphy_base,
data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
mask |= SD_EXTERNAL_CONFIG1_TX_IDLE_MASK;
data |= 0x1 << SD_EXTERNAL_CONFIG1_TX_IDLE_OFFSET;
reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
/* Wait 1ms - until band gap and ref clock ready */
mdelay(1);
/*
* Erratum IPCE_COMPHY-1353: toggle TX_IDLE bit in
* addition to the PHY reset
*/
mask = SD_EXTERNAL_CONFIG1_TX_IDLE_MASK;
data = 0x0U;
reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
/* Start comphy Configuration */
debug("stage: Comphy configuration\n");
/* set reference clock */
@ -1885,6 +1922,7 @@ static int mvebu_cp110_comphy_usb3_power_on(uint64_t comphy_base,
{
uintptr_t hpipe_addr, comphy_addr, addr;
uint32_t mask, data;
uint8_t ap_nr, cp_nr, phy_polarity_invert;
int ret = 0;
debug_enter();
@ -1893,6 +1931,13 @@ static int mvebu_cp110_comphy_usb3_power_on(uint64_t comphy_base,
mvebu_cp110_comphy_set_pipe_selector(comphy_base, comphy_index,
comphy_mode);
mvebu_cp110_get_ap_and_cp_nr(&ap_nr, &cp_nr, comphy_base);
const struct usb_params *usb_static_values =
&usb_static_values_tab[ap_nr][cp_nr][comphy_index];
phy_polarity_invert = usb_static_values->polarity_invert;
hpipe_addr = HPIPE_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base),
comphy_index);
comphy_addr = COMPHY_ADDR(comphy_base, comphy_index);
@ -1972,6 +2017,13 @@ static int mvebu_cp110_comphy_usb3_power_on(uint64_t comphy_base,
0x1 << HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET,
HPIPE_TST_MODE_CTRL_MODE_MARGIN_MASK);
/* The polarity inversion for USB was not tested due to lack of hw
* design which requires it. Support is added for customer needs.
*/
if (phy_polarity_invert)
mvebu_cp110_polarity_invert(hpipe_addr + HPIPE_SYNC_PATTERN_REG,
phy_polarity_invert);
/* Start analog parameters from ETP(HW) */
debug("stage: Analog parameters from ETP(HW)\n");
/* Set Pin DFE_PAT_DIS -> Bit[1]: PIN_DFE_PAT_DIS = 0x0 */

10
drivers/marvell/comphy/phy-comphy-cp110.h
View File

@ -76,9 +76,15 @@ struct sata_params {
uint8_t g2_rx_selmupi;
uint8_t g3_rx_selmupi;
uint8_t polarity_invert;
_Bool valid;
};
struct usb_params {
uint8_t polarity_invert;
};
int mvebu_cp110_comphy_is_pll_locked(uint64_t comphy_base,
uint8_t comphy_index);
int mvebu_cp110_comphy_power_off(uint64_t comphy_base,
@ -89,3 +95,7 @@ int mvebu_cp110_comphy_xfi_rx_training(uint64_t comphy_base,
uint8_t comphy_index);
int mvebu_cp110_comphy_digital_reset(uint64_t comphy_base, uint8_t comphy_index,
uint32_t comphy_mode, uint32_t command);
#define COMPHY_POLARITY_NO_INVERT 0
#define COMPHY_POLARITY_TXD_INVERT 1
#define COMPHY_POLARITY_RXD_INVERT 2

8
drivers/marvell/comphy/phy-default-porting-layer.h
View File

@ -45,7 +45,15 @@ static const struct sata_params
.g3_rx_selmupf = 0x2,
.g1_rx_selmupi = 0x0, .g2_rx_selmupi = 0x0,
.g3_rx_selmupi = 0x2,
.polarity_invert = COMPHY_POLARITY_NO_INVERT,
.valid = 0x1
},
};
static const struct usb_params
usb_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = {
[0 ... AP_NUM-1][0 ... CP_NUM-1][0 ... MAX_LANE_NR-1] = {
.polarity_invert = COMPHY_POLARITY_NO_INVERT
},
};
#endif /* PHY_DEFAULT_PORTING_LAYER_H */

43
drivers/marvell/mochi/ap807_setup.c
View File

@ -47,6 +47,14 @@
SEC_MOCHI_IN_ACC_IHB1_EN | \
SEC_MOCHI_IN_ACC_IHB2_EN | \
SEC_MOCHI_IN_ACC_PIDI_EN)
#define MOCHI_IN_ACC_LEVEL_FORCE_NONSEC (0)
#define MOCHI_IN_ACC_LEVEL_FORCE_SEC (1)
#define MOCHI_IN_ACC_LEVEL_LEAVE_ORIG (2)
#define MOCHI_IN_ACC_LEVEL_MASK_ALL (3)
#define SEC_MOCHI_IN_ACC_IHB0_LEVEL(l) ((l) << 1)
#define SEC_MOCHI_IN_ACC_IHB1_LEVEL(l) ((l) << 4)
#define SEC_MOCHI_IN_ACC_PIDI_LEVEL(l) ((l) << 10)
/* SYSRST_OUTn Config definitions */
#define MVEBU_SYSRST_OUT_CONFIG_REG (MVEBU_MISC_SOC_BASE + 0x4)
@ -71,19 +79,36 @@ enum axi_attr {
static void ap_sec_masters_access_en(uint32_t enable)
{
uint32_t reg;
/* Open/Close incoming access for all masters.
* The access is disabled in trusted boot mode
* Could only be done in EL3
*/
reg = mmio_read_32(SEC_MOCHI_IN_ACC_REG);
if (enable)
mmio_write_32(SEC_MOCHI_IN_ACC_REG, reg |
SEC_IN_ACCESS_ENA_ALL_MASTERS);
else
mmio_write_32(SEC_MOCHI_IN_ACC_REG,
reg & ~SEC_IN_ACCESS_ENA_ALL_MASTERS);
if (enable != 0) {
mmio_clrsetbits_32(SEC_MOCHI_IN_ACC_REG, 0x0U, /* no clear */
SEC_IN_ACCESS_ENA_ALL_MASTERS);
#if LLC_SRAM
/* Do not change access security level
* for PIDI masters
*/
mmio_clrsetbits_32(SEC_MOCHI_IN_ACC_REG,
SEC_MOCHI_IN_ACC_PIDI_LEVEL(
MOCHI_IN_ACC_LEVEL_MASK_ALL),
SEC_MOCHI_IN_ACC_PIDI_LEVEL(
MOCHI_IN_ACC_LEVEL_LEAVE_ORIG));
#endif
} else {
mmio_clrsetbits_32(SEC_MOCHI_IN_ACC_REG,
SEC_IN_ACCESS_ENA_ALL_MASTERS,
0x0U /* no set */);
#if LLC_SRAM
/* Return PIDI access level to the default */
mmio_clrsetbits_32(SEC_MOCHI_IN_ACC_REG,
SEC_MOCHI_IN_ACC_PIDI_LEVEL(
MOCHI_IN_ACC_LEVEL_MASK_ALL),
SEC_MOCHI_IN_ACC_PIDI_LEVEL(
MOCHI_IN_ACC_LEVEL_FORCE_NONSEC));
#endif
}
}
static void setup_smmu(void)

41
drivers/marvell/mochi/apn806_setup.c
View File

@ -41,6 +41,14 @@
SEC_MOCHI_IN_ACC_IHB1_EN | \
SEC_MOCHI_IN_ACC_IHB2_EN | \
SEC_MOCHI_IN_ACC_PIDI_EN)
#define MOCHI_IN_ACC_LEVEL_FORCE_NONSEC (0)
#define MOCHI_IN_ACC_LEVEL_FORCE_SEC (1)
#define MOCHI_IN_ACC_LEVEL_LEAVE_ORIG (2)
#define MOCHI_IN_ACC_LEVEL_MASK_ALL (3)
#define SEC_MOCHI_IN_ACC_IHB0_LEVEL(l) ((l) << 1)
#define SEC_MOCHI_IN_ACC_IHB1_LEVEL(l) ((l) << 4)
#define SEC_MOCHI_IN_ACC_PIDI_LEVEL(l) ((l) << 10)
/* SYSRST_OUTn Config definitions */
#define MVEBU_SYSRST_OUT_CONFIG_REG (MVEBU_MISC_SOC_BASE + 0x4)
@ -67,19 +75,36 @@ enum axi_attr {
static void apn_sec_masters_access_en(uint32_t enable)
{
uint32_t reg;
/* Open/Close incoming access for all masters.
* The access is disabled in trusted boot mode
* Could only be done in EL3
*/
reg = mmio_read_32(SEC_MOCHI_IN_ACC_REG);
if (enable)
mmio_write_32(SEC_MOCHI_IN_ACC_REG, reg |
if (enable != 0) {
mmio_clrsetbits_32(SEC_MOCHI_IN_ACC_REG, 0x0U, /* no clear */
SEC_IN_ACCESS_ENA_ALL_MASTERS);
else
mmio_write_32(SEC_MOCHI_IN_ACC_REG, reg &
~SEC_IN_ACCESS_ENA_ALL_MASTERS);
#if LLC_SRAM
/* Do not change access security level
* for PIDI masters
*/
mmio_clrsetbits_32(SEC_MOCHI_IN_ACC_REG,
SEC_MOCHI_IN_ACC_PIDI_LEVEL(
MOCHI_IN_ACC_LEVEL_MASK_ALL),
SEC_MOCHI_IN_ACC_PIDI_LEVEL(
MOCHI_IN_ACC_LEVEL_LEAVE_ORIG));
#endif
} else {
mmio_clrsetbits_32(SEC_MOCHI_IN_ACC_REG,
SEC_IN_ACCESS_ENA_ALL_MASTERS,
0x0U /* no set */);
#if LLC_SRAM
/* Return PIDI access level to the default */
mmio_clrsetbits_32(SEC_MOCHI_IN_ACC_REG,
SEC_MOCHI_IN_ACC_PIDI_LEVEL(
MOCHI_IN_ACC_LEVEL_MASK_ALL),
SEC_MOCHI_IN_ACC_PIDI_LEVEL(
MOCHI_IN_ACC_LEVEL_FORCE_NONSEC));
#endif
}
}
static void setup_smmu(void)

2
plat/marvell/armada/a3k/common/a3700_common.mk
View File

@ -138,7 +138,7 @@ endif
@mv -t $(BUILD_PLAT)/$(BUILD_UART) $(TIM_IMAGE) $(DOIMAGE_CFG) $(TIMN_IMAGE) $(TIMNCFG)
@find . -name "*_h.*" |xargs cp -ut $(BUILD_PLAT)/$(BUILD_UART)
@mv $(subst .bin,_h.bin,$(WTMI_MULTI_IMG)) $(BUILD_PLAT)/$(BUILD_UART)/wtmi_h.bin
@tar czf $(BUILD_PLAT)/$(BUILD_UART).tgz -C $(BUILD_PLAT) ./$(BUILD_UART)
@tar czf $(BUILD_PLAT)/$(BUILD_UART).tgz.bin -C $(BUILD_PLAT) ./$(BUILD_UART)
@echo
@echo "Building flash image"
$(TIMBUILD) $(TIMBLDARGS)

8
plat/marvell/armada/a3k/common/include/platform_def.h
View File

@ -70,6 +70,14 @@
* PLAT_MARVELL_FIP_BASE = 0x4120000
*/
/*
* Since BL33 is loaded by BL2 (and validated by BL31) to DRAM offset 0,
* it is allowed to load/copy images to 'NULL' pointers
*/
#if defined(IMAGE_BL2) || defined(IMAGE_BL31)
#define PLAT_ALLOW_ZERO_ADDR_COPY
#endif
#define PLAT_MARVELL_ATF_BASE 0x4000000
#define PLAT_MARVELL_ATF_LOAD_ADDR \
(PLAT_MARVELL_ATF_BASE + 0x100000)

11
plat/marvell/armada/a8k/a80x0/board/phy-porting-layer.h
View File

@ -92,6 +92,7 @@ static const struct sata_params
.g3_rx_selmupf = 0x2,
.g1_rx_selmupi = 0x0, .g2_rx_selmupi = 0x0,
.g3_rx_selmupi = 0x2,
.polarity_invert = COMPHY_POLARITY_NO_INVERT,
.valid = 0x1
}, /* Comphy1 */
{ 0 }, /* Comphy2 */
@ -116,6 +117,7 @@ static const struct sata_params
.g3_rx_selmupf = 0x2,
.g1_rx_selmupi = 0x0, .g2_rx_selmupi = 0x0,
.g3_rx_selmupi = 0x2,
.polarity_invert = COMPHY_POLARITY_NO_INVERT,
.valid = 0x1
}, /* Comphy3 */
{ 0 }, /* Comphy4 */
@ -146,6 +148,7 @@ static const struct sata_params
.g3_rx_selmupf = 0x2,
.g1_rx_selmupi = 0x0, .g2_rx_selmupi = 0x0,
.g3_rx_selmupi = 0x2,
.polarity_invert = COMPHY_POLARITY_NO_INVERT,
.valid = 0x1
}, /* Comphy1 */
{ 0 }, /* Comphy2 */
@ -170,6 +173,7 @@ static const struct sata_params
.g3_rx_selmupf = 0x2,
.g1_rx_selmupi = 0x0, .g2_rx_selmupi = 0x0,
.g3_rx_selmupi = 0x2,
.polarity_invert = COMPHY_POLARITY_NO_INVERT,
.valid = 0x1
}, /* Comphy3 */
{ 0 }, /* Comphy4 */
@ -178,4 +182,11 @@ static const struct sata_params
},
},
};
static const struct usb_params
usb_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = {
[0 ... AP_NUM-1][0 ... CP_NUM-1][0 ... MAX_LANE_NR-1] = {
.polarity_invert = COMPHY_POLARITY_NO_INVERT
},
};
#endif /* PHY_PORTING_LAYER_H */

32
plat/marvell/armada/a8k/common/aarch64/plat_arch_config.c
View File

@ -15,6 +15,13 @@
#define MVEBU_IO_AFFINITY (0xF00)
#define MVEBU_SF_REG (MVEBU_REGS_BASE + 0x40)
#define MVEBU_SF_EN BIT(8)
#define MVEBU_DFX_REG(cluster_id) (MVEBU_REGS_BASE + 0x6F82A0 + \
(cluster_id) * 0x4)
#define MVEBU_DFX_CLK_EN_POS 0x3
#define MVEBU_DFX_CL0_CLK_OFFS 16
#define MVEBU_DFX_CL0_CLK_MASK (0xF << MVEBU_DFX_CL0_CLK_OFFS)
#define MVEBU_DFX_CL1_CLK_OFFS 8
#define MVEBU_DFX_CL1_CLK_MASK (0xF << MVEBU_DFX_CL1_CLK_OFFS)
#ifdef MVEBU_SOC_AP807
static void plat_enable_snoop_filter(void)
@ -29,6 +36,29 @@ static void plat_enable_snoop_filter(void)
}
#endif
#ifndef MVEBU_SOC_AP807
static void plat_config_dfx_clock(void)
{
int cluster_id = plat_my_core_pos();
uint32_t val;
/* DFX clock needs to be configured once per cluster */
if ((cluster_id % PLAT_MAX_CPUS_PER_CLUSTER) != 0) {
return;
}
val = mmio_read_32(MVEBU_DFX_REG(cluster_id / PLAT_MAX_CPUS_PER_CLUSTER));
if (cluster_id == 0) {
val &= ~MVEBU_DFX_CL0_CLK_MASK;
val |= (MVEBU_DFX_CLK_EN_POS << MVEBU_DFX_CL0_CLK_OFFS);
} else {
val &= ~MVEBU_DFX_CL1_CLK_MASK;
val |= (MVEBU_DFX_CLK_EN_POS << MVEBU_DFX_CL1_CLK_OFFS);
}
mmio_write_32(MVEBU_DFX_REG(cluster_id / PLAT_MAX_CPUS_PER_CLUSTER), val);
}
#endif
static void plat_enable_affinity(void)
{
int cluster_id;
@ -59,5 +89,7 @@ void marvell_psci_arch_init(int die_index)
#ifdef MVEBU_SOC_AP807
plat_enable_snoop_filter();
#else
plat_config_dfx_clock();
#endif
}

2
plat/marvell/armada/a8k/common/include/platform_def.h
View File

@ -92,6 +92,8 @@
#define PLAT_MARVELL_CORE_COUNT (PLAT_MARVELL_CLUSTER_COUNT * \
PLAT_MARVELL_CLUSTER_CORE_COUNT)
#define PLAT_MAX_CPUS_PER_CLUSTER PLAT_MARVELL_CLUSTER_CORE_COUNT
/* Part of DRAM that is used as Trusted ROM */
#define PLAT_MARVELL_TRUSTED_ROM_BASE PLAT_MARVELL_ATF_LOAD_ADDR
/* 4 MB for FIP image */

7
plat/marvell/octeontx/otx2/t91/t9130/board/phy-porting-layer.h
View File

@ -131,8 +131,15 @@ SATA_PARAMS sata_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = {
.g3_rx_selmupf = 0x2,
.g1_rx_selmupi = 0x0, .g2_rx_selmupi = 0x0,
.g3_rx_selmupi = 0x2,
.polarity_invert = COMPHY_POLARITY_NO_INVERT,
.valid = 0x1
},
};
static const struct usb_params
usb_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = {
[0 ... AP_NUM-1][0 ... CP_NUM-1][0 ... MAX_LANE_NR-1] = {
.polarity_invert = COMPHY_POLARITY_NO_INVERT
},
};
#endif /* __PHY_PORTING_LAYER_H */