Merge changes from topic "erratas" into integration
* changes: errata: workaround for Neoverse N2 erratum 2138956 errata: workaround for Neoverse N2 erratum 2189731 errata: workaround for Cortex-A710 erratum 2017096 errata: workaround for Cortex-A710 erratum 2055002
This commit is contained in:
Madhukar Pappireddy
TrustedFirmware Code Review
commit
ef03e78f42
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@ -381,6 +381,14 @@ For Cortex-A710, the following errata build flags are defined :
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Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
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r2p0 of the CPU. It is still open.
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- ``ERRATA_A710_2055002``: This applies errata 2055002 workaround to
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Cortex-A710 CPU. This needs to be enabled for revisions r1p0, r2p0 of the CPU
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and is still open.
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- ``ERRATA_A710_2017096``: This applies errata 2017096 workaround to
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Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
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of the CPU and is still open.
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For Neoverse N2, the following errata build flags are defined :
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- ``ERRATA_N2_2067956``: This applies errata 2067956 workaround to Neoverse-N2
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@ -389,6 +397,12 @@ For Neoverse N2, the following errata build flags are defined :
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- ``ERRATA_N2_2025414``: This applies errata 2025414 workaround to Neoverse-N2
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CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
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- ``ERRATA_N2_2189731``: This applies errata 2189731 workaround to Neoverse-N2
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CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
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- ``ERRATA_N2_2138956``: This applies errata 2138956 workaround to Neoverse-N2
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CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
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DSU Errata Workarounds
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----------------------
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@ -13,6 +13,7 @@
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* CPU Extended Control register specific definitions
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******************************************************************************/
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#define CORTEX_A710_CPUECTLR_EL1 S3_0_C15_C1_4
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#define CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8)
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/*******************************************************************************
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* CPU Power Control register specific definitions
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@ -20,4 +21,10 @@
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#define CORTEX_A710_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_A710_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A710_CPUACTLR_EL1 S3_0_C15_C1_0
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#define CORTEX_A710_CPUACTLR_EL1_BIT_46 (ULL(1) << 46)
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#endif /* CORTEX_A710_H */
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@ -35,4 +35,10 @@
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#define NEOVERSE_N2_CPUACTLR2_EL1 S3_0_C15_C1_1
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#define NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2)
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/*******************************************************************************
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* CPU Auxiliary Control register 5 specific definitions.
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******************************************************************************/
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#define NEOVERSE_N2_CPUACTLR5_EL1 S3_0_C15_C8_0
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#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 (ULL(1) << 44)
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#endif /* NEOVERSE_N2_H */
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@ -107,6 +107,59 @@ func check_errata_2081180
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b cpu_rev_var_ls
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endfunc check_errata_2081180
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/* ---------------------------------------------------------------------
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* Errata Workaround for Cortex-A710 Erratum 2055002.
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* This applies to revision r1p0, r2p0 of Cortex-A710 and is still open.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* ---------------------------------------------------------------------
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*/
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func errata_a710_2055002_wa
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/* Compare x0 against revision r2p0 */
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mov x17, x30
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bl check_errata_2055002
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cbz x0, 1f
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mrs x1, CORTEX_A710_CPUACTLR_EL1
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orr x1, x1, CORTEX_A710_CPUACTLR_EL1_BIT_46
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msr CORTEX_A710_CPUACTLR_EL1, x1
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1:
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ret x17
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endfunc errata_a710_2055002_wa
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func check_errata_2055002
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/* Applies to r1p0, r2p0 */
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mov x1, #0x20
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b cpu_rev_var_ls
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endfunc check_errata_2055002
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/* -------------------------------------------------------------
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* Errata Workaround for Cortex-A710 Erratum 2017096.
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* This applies to revisions r0p0, r1p0 and r2p0 of Cortex-A710.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* -------------------------------------------------------------
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*/
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func errata_a710_2017096_wa
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/* Compare x0 against revision r0p0 to r2p0 */
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mov x17, x30
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bl check_errata_2017096
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cbz x0, 1f
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mrs x1, CORTEX_A710_CPUECTLR_EL1
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orr x1, x1, CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT
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msr CORTEX_A710_CPUECTLR_EL1, x1
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1:
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ret x17
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endfunc errata_a710_2017096_wa
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func check_errata_2017096
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/* Applies to r0p0, r1p0, r2p0 */
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mov x1, #0x20
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b cpu_rev_var_ls
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endfunc check_errata_2017096
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/* ----------------------------------------------------
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* HW will do the cache maintenance while powering down
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* ----------------------------------------------------
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@ -123,10 +176,10 @@ func cortex_a710_core_pwr_dwn
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ret
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endfunc cortex_a710_core_pwr_dwn
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/*
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* Errata printing function for Cortex A710. Must follow AAPCS.
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*/
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#if REPORT_ERRATA
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/*
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* Errata printing function for Cortex-A710. Must follow AAPCS.
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*/
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func cortex_a710_errata_report
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stp x8, x30, [sp, #-16]!
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@ -139,6 +192,8 @@ func cortex_a710_errata_report
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*/
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report_errata ERRATA_A710_1987031, cortex_a710, 1987031
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report_errata ERRATA_A710_2081180, cortex_a710, 2081180
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report_errata ERRATA_A710_2055002, cortex_a710, 2055002
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report_errata ERRATA_A710_2017096, cortex_a710, 2017096
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ldp x8, x30, [sp], #16
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ret
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@ -164,8 +219,17 @@ func cortex_a710_reset_func
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bl errata_a710_2081180_wa
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#endif
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#if ERRATA_A710_2055002
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mov x0, x18
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bl errata_a710_2055002_wa
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#endif
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#if ERRATA_A710_2017096
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mov x0, x18
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bl errata_a710_2017096_wa
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#endif
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isb
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ret x19
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ret x19
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endfunc cortex_a710_reset_func
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/* ---------------------------------------------
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@ -114,6 +114,75 @@ func check_errata_2025414
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b cpu_rev_var_ls
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endfunc check_errata_2025414
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/* ---------------------------------------------------------------
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* Errata Workaround for Neoverse N2 Erratum 2189731.
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* This applies to revision r0p0 of Neoverse N2 and is still open.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* ---------------------------------------------------------------
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*/
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func errata_n2_2189731_wa
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/* Compare x0 against revision r0p0 */
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mov x17, x30
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bl check_errata_2189731
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cbz x0, 1f
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mrs x1, NEOVERSE_N2_CPUACTLR5_EL1
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orr x1, x1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_44
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msr NEOVERSE_N2_CPUACTLR5_EL1, x1
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1:
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ret x17
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endfunc errata_n2_2189731_wa
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func check_errata_2189731
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/* Applies to r0p0 */
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mov x1, #0x00
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b cpu_rev_var_ls
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endfunc check_errata_2189731
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/* --------------------------------------------------
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* Errata Workaround for Neoverse N2 Erratum 2138956.
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* This applies to revision r0p0 of Neoverse N2. it is still open.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_n2_2138956_wa
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/* Check revision. */
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mov x17, x30
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bl check_errata_2138956
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cbz x0, 1f
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/* Apply instruction patching sequence */
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ldr x0,=0x3
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msr S3_6_c15_c8_0,x0
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ldr x0,=0xF3A08002
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msr S3_6_c15_c8_2,x0
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ldr x0,=0xFFF0F7FE
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msr S3_6_c15_c8_3,x0
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ldr x0,=0x10002001003FF
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msr S3_6_c15_c8_1,x0
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ldr x0,=0x4
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msr S3_6_c15_c8_0,x0
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ldr x0,=0xBF200000
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msr S3_6_c15_c8_2,x0
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ldr x0,=0xFFEF0000
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msr S3_6_c15_c8_3,x0
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ldr x0,=0x10002001003F3
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msr S3_6_c15_c8_1,x0
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isb
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1:
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ret x17
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endfunc errata_n2_2138956_wa
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func check_errata_2138956
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/* Applies to r0p0 */
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mov x1, #0x00
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b cpu_rev_var_ls
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endfunc check_errata_2138956
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/* -------------------------------------------
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* The CPU Ops reset function for Neoverse N2.
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* -------------------------------------------
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@ -144,6 +213,17 @@ func neoverse_n2_reset_func
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bl errata_n2_2025414_wa
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#endif
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#if ERRATA_N2_2189731
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mov x0, x18
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bl errata_n2_2189731_wa
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#endif
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#if ERRATA_N2_2138956
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mov x0, x18
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bl errata_n2_2138956_wa
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#endif
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#if ENABLE_AMU
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/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
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mrs x0, cptr_el3
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@ -207,6 +287,8 @@ func neoverse_n2_errata_report
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report_errata ERRATA_N2_2002655, neoverse_n2, 2002655
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report_errata ERRATA_N2_2067956, neoverse_n2, 2067956
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report_errata ERRATA_N2_2025414, neoverse_n2, 2025414
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report_errata ERRATA_N2_2189731, neoverse_n2, 2189731
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report_errata ERRATA_N2_2138956, neoverse_n2, 2138956
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ldp x8, x30, [sp], #16
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ret
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@ -433,6 +433,22 @@ ERRATA_N2_2067956 ?=0
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# to revision r0p0 of the Neoverse N2 cpu and is still open.
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ERRATA_N2_2025414 ?=0
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# Flag to apply erratum 2189731 workaround during reset. This erratum applies
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# to revision r0p0 of the Neoverse N2 cpu and is still open.
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ERRATA_N2_2189731 ?=0
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# Flag to apply erratum 2138956 workaround during reset. This erratum applies
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# to revision r0p0 of the Neoverse N2 cpu and is still open.
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ERRATA_N2_2138956 ?=0
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# Flag to apply erratum 2055002 workaround during reset. This erratum applies
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# to revision r1p0, r2p0 of the Cortex-A710 cpu and is still open.
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ERRATA_A710_2055002 ?=0
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# Flag to apply erratum 2017096 workaround during reset. This erratum applies
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# to revision r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is still open.
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ERRATA_A710_2017096 ?=0
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# Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0.
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# Applying the workaround results in higher DSU power consumption on idle.
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ERRATA_DSU_798953 ?=0
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@ -798,6 +814,22 @@ $(eval $(call add_define,ERRATA_N2_2067956))
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$(eval $(call assert_boolean,ERRATA_N2_2025414))
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$(eval $(call add_define,ERRATA_N2_2025414))
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# Process ERRATA_N2_2189731 flag
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$(eval $(call assert_boolean,ERRATA_N2_2189731))
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$(eval $(call add_define,ERRATA_N2_2189731))
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# Process ERRATA_N2_2138956 flag
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$(eval $(call assert_boolean,ERRATA_N2_2138956))
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$(eval $(call add_define,ERRATA_N2_2138956))
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# Process ERRATA_A710_2055002 flag
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$(eval $(call assert_boolean,ERRATA_A710_2055002))
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$(eval $(call add_define,ERRATA_A710_2055002))
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# Process ERRATA_A710_2017096 flag
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$(eval $(call assert_boolean,ERRATA_A710_2017096))
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$(eval $(call add_define,ERRATA_A710_2017096))
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# Process ERRATA_DSU_798953 flag
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$(eval $(call assert_boolean,ERRATA_DSU_798953))
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$(eval $(call add_define,ERRATA_DSU_798953))
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