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rockchip: rk3399: restore PMU_CRU_GATEDIS_CON0 value after ddr dvfs 

we will set PMU_CRU_GATEDIS_CON0 when idle port, it will enable
all clock, for save power consumption, we need to restore old value
when finish it.

Signed-off-by: Lin Huang <hl@rock-chips.com>
This commit is contained in:
Lin Huang 2016-12-30 11:50:01 +08:00 committed by Xing Zheng
parent 87b5c17f91
commit ef0a6bfc69
1 changed files with 6 additions and 0 deletions
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6
plat/rockchip/rk3399/drivers/m0/src/dram.c
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@ -112,6 +112,8 @@
#define CIC_CTRL1 0x4
#define CIC_STATUS0 0x10
uint32_t gatedis_con0;
static inline int check_dma_status(uint32_t vop_addr, uint32_t *clr_dma_flag)
{
if (*clr_dma_flag) {
@ -182,6 +184,7 @@ out:
static void idle_port(void)
{
gatedis_con0 = mmio_read_32(PMU_CRU_BASE_ADDR + PMU_CRU_GATEDIS_CON0);
mmio_write_32(PMU_CRU_BASE_ADDR + PMU_CRU_GATEDIS_CON0, 0x3fffffff);
mmio_setbits_32(PMU_BASE + PMU_BUS_IDLE_REQ,
IDLE_REQ_MSCH0 | IDLE_REQ_MSCH1);
@ -197,6 +200,9 @@ static void deidle_port(void)
while (mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST) &
(IDLE_MSCH1 | IDLE_MSCH0))
continue;
/* document is wrong, PMU_CRU_GATEDIS_CON0 do not need set MASK BIT */
mmio_write_32(PMU_CRU_BASE_ADDR + PMU_CRU_GATEDIS_CON0, gatedis_con0);
}
static void ddr_set_pll(void)