rockchip: rk3399: restore PMU_CRU_GATEDIS_CON0 value after ddr dvfs
we will set PMU_CRU_GATEDIS_CON0 when idle port, it will enable all clock, for save power consumption, we need to restore old value when finish it. Signed-off-by: Lin Huang <hl@rock-chips.com>
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@ -112,6 +112,8 @@
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#define CIC_CTRL1 0x4
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#define CIC_CTRL1 0x4
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#define CIC_STATUS0 0x10
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#define CIC_STATUS0 0x10
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uint32_t gatedis_con0;
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static inline int check_dma_status(uint32_t vop_addr, uint32_t *clr_dma_flag)
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static inline int check_dma_status(uint32_t vop_addr, uint32_t *clr_dma_flag)
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{
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{
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if (*clr_dma_flag) {
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if (*clr_dma_flag) {
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@ -182,6 +184,7 @@ out:
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static void idle_port(void)
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static void idle_port(void)
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{
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{
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gatedis_con0 = mmio_read_32(PMU_CRU_BASE_ADDR + PMU_CRU_GATEDIS_CON0);
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mmio_write_32(PMU_CRU_BASE_ADDR + PMU_CRU_GATEDIS_CON0, 0x3fffffff);
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mmio_write_32(PMU_CRU_BASE_ADDR + PMU_CRU_GATEDIS_CON0, 0x3fffffff);
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mmio_setbits_32(PMU_BASE + PMU_BUS_IDLE_REQ,
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mmio_setbits_32(PMU_BASE + PMU_BUS_IDLE_REQ,
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IDLE_REQ_MSCH0 | IDLE_REQ_MSCH1);
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IDLE_REQ_MSCH0 | IDLE_REQ_MSCH1);
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@ -197,6 +200,9 @@ static void deidle_port(void)
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while (mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST) &
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while (mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST) &
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(IDLE_MSCH1 | IDLE_MSCH0))
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(IDLE_MSCH1 | IDLE_MSCH0))
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continue;
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continue;
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/* document is wrong, PMU_CRU_GATEDIS_CON0 do not need set MASK BIT */
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mmio_write_32(PMU_CRU_BASE_ADDR + PMU_CRU_GATEDIS_CON0, gatedis_con0);
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}
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}
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static void ddr_set_pll(void)
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static void ddr_set_pll(void)
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