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Add myself and Andre Przywara as code owners for the Arm FPGA platform port 

Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I6d3949a971fada5a086b788dbe274f8451fcfc0d
This commit is contained in:
Javier Almansa Sobrino 2020-07-10 10:34:04 +01:00
parent 99c447f440
commit f0e2e66ac6
1 changed files with 8 additions and 0 deletions
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docs/about/maintainers.rst
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@ -320,6 +320,14 @@ Amlogic Meson A113D (AXG) platform port
:F: docs/plat/meson-axg.rst
:F: plat/amlogic/axg/
Arm FPGA platform port
^^^^^^^^^^^^^^^^^^^^^^
:M: Andre Przywara <andre.przywara@arm.com>
:G: `Andre-ARM`_
:M: Javier Almansa Sobrino <Javier.AlmansaSobrino@arm.com>
:G: `javieralso-arm`_
:F: plat/arm/board/arm_fpga
Arm System Guidance for Infrastructure / Mobile FVP platforms
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
:M: Nariman Poushin <nariman.poushin@linaro.org>