andrius
/
arm-trusted-firmware
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

PIE: Use PC relative adrp/adr for symbol reference 

This patch fixes up the AArch64 assembly code to use
adrp/adr instructions instead of ldr instruction for
reference to symbols. This allows these assembly
sequences to be Position Independant. Note that the
the reference to sizes have been replaced with
calculation of size at runtime. This is because size
is a constant value and does not depend on execution
address and using PC relative instructions for loading
them makes them relative to execution address. Also
we cannot use `ldr` instruction to load size as it
generates a dynamic relocation entry which must *not*
be fixed up and it is difficult for a dynamic loader
to differentiate which entries need to be skipped.

Change-Id: I8bf4ed5c58a9703629e5498a27624500ef40a836
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
This commit is contained in:
Soby Mathew 2018-10-12 16:40:28 +01:00
parent 3bd17c0fef
commit f1722b693d
6 changed files with 53 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
bl2/aarch64/bl2_entrypoint.S
View File

@ -70,13 +70,19 @@ func bl2_entrypoint
* - the coherent memory section. * - the coherent memory section.
* --------------------------------------------- * ---------------------------------------------
*/ */
ldr x0, =__BSS_START__ adrp x0, __BSS_START__
ldr x1, =__BSS_SIZE__ add x0, x0, :lo12:__BSS_START__
adrp x1, __BSS_END__
add x1, x1, :lo12:__BSS_END__
sub x1, x1, x0
bl zeromem bl zeromem
#if USE_COHERENT_MEM #if USE_COHERENT_MEM
ldr x0, =__COHERENT_RAM_START__ adrp x0, __COHERENT_RAM_START__
ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__ add x0, x0, :lo12:__COHERENT_RAM_START__
adrp x1, __COHERENT_RAM_END_UNALIGNED__
add x1, x1, :lo12:__COHERENT_RAM_END_UNALIGNED__
sub x1, x1, x0
bl zeromem bl zeromem
#endif #endif

8
include/common/aarch64/asm_macros.S
View File

@ -105,8 +105,9 @@
* Clobber: X30, X1, X2 * Clobber: X30, X1, X2
*/ */
.macro get_my_mp_stack _name, _size .macro get_my_mp_stack _name, _size
bl plat_my_core_pos bl plat_my_core_pos
ldr x2, =(\_name + \_size) adrp x2, (\_name + \_size)
add x2, x2, :lo12:(\_name + \_size)
mov x1, #\_size mov x1, #\_size
madd x0, x0, x1, x2 madd x0, x0, x1, x2
.endm .endm
@ -117,7 +118,8 @@
* Out: X0 = physical address of stack base * Out: X0 = physical address of stack base
*/ */
.macro get_up_stack _name, _size .macro get_up_stack _name, _size
ldr x0, =(\_name + \_size) adrp x0, (\_name + \_size)
add x0, x0, :lo12:(\_name + \_size)
.endm .endm
/* /*

30
include/common/aarch64/el3_common_macros.S
View File

@ -283,26 +283,38 @@
* an earlier boot loader stage. * an earlier boot loader stage.
* ------------------------------------------------------------- * -------------------------------------------------------------
*/ */
ldr x0, =__RW_START__ adrp x0, __RW_START__
ldr x1, =__RW_END__ add x0, x0, :lo12:__RW_START__
adrp x1, __RW_END__
add x1, x1, :lo12:__RW_END__
sub x1, x1, x0 sub x1, x1, x0
bl inv_dcache_range bl inv_dcache_range
#endif #endif
adrp x0, __BSS_START__
add x0, x0, :lo12:__BSS_START__
ldr x0, =__BSS_START__ adrp x1, __BSS_END__
ldr x1, =__BSS_SIZE__ add x1, x1, :lo12:__BSS_END__
sub x1, x1, x0
bl zeromem bl zeromem
#if USE_COHERENT_MEM #if USE_COHERENT_MEM
ldr x0, =__COHERENT_RAM_START__ adrp x0, __COHERENT_RAM_START__
ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__ add x0, x0, :lo12:__COHERENT_RAM_START__
adrp x1, __COHERENT_RAM_END_UNALIGNED__
add x1, x1, :lo12: __COHERENT_RAM_END_UNALIGNED__
sub x1, x1, x0
bl zeromem bl zeromem
#endif #endif
#if defined(IMAGE_BL1) || (defined(IMAGE_BL2) && BL2_IN_XIP_MEM) #if defined(IMAGE_BL1) || (defined(IMAGE_BL2) && BL2_IN_XIP_MEM)
ldr x0, =__DATA_RAM_START__ adrp x0, __DATA_RAM_START__
ldr x1, =__DATA_ROM_START__ add x0, x0, :lo12:__DATA_RAM_START__
ldr x2, =__DATA_SIZE__ adrp x1, __DATA_ROM_START__
add x1, x1, :lo12:__DATA_ROM_START__
adrp x2, __DATA_RAM_END__
add x2, x2, :lo12:__DATA_RAM_END__
sub x2, x2, x0
bl memcpy16 bl memcpy16
#endif #endif
.endif /* _init_c_runtime */ .endif /* _init_c_runtime */

6
include/lib/pmf/pmf_asm_macros.S
View File

@ -18,10 +18,12 @@
mov x9, x30 mov x9, x30
bl plat_my_core_pos bl plat_my_core_pos
mov x30, x9 mov x30, x9
ldr x1, =__PERCPU_TIMESTAMP_SIZE__ adr x2, __PMF_PERCPU_TIMESTAMP_END__
adr x1, __PMF_TIMESTAMP_START__
sub x1, x2, x1
mov x2, #(\_tid * PMF_TS_SIZE) mov x2, #(\_tid * PMF_TS_SIZE)
madd x0, x0, x1, x2 madd x0, x0, x1, x2
ldr x1, =pmf_ts_mem_\_name adr x1, pmf_ts_mem_\_name
add x0, x0, x1 add x0, x0, x1
.endm .endm

16
lib/romlib/init.s
View File

@ -5,7 +5,7 @@
*/ */
.globl rom_lib_init .globl rom_lib_init
.extern __DATA_RAM_START__, __DATA_ROM_START__, __DATA_SIZE__ .extern __DATA_RAM_START__, __DATA_ROM_START__, __DATA_RAM_END__
.extern memset, memcpy .extern memset, memcpy
rom_lib_init: rom_lib_init:
@ -16,13 +16,19 @@ rom_lib_init:
1: stp x29, x30, [sp, #-16]! 1: stp x29, x30, [sp, #-16]!
adrp x0, __DATA_RAM_START__ adrp x0, __DATA_RAM_START__
ldr x1,= __DATA_ROM_START__ adrp x1, __DATA_ROM_START__
ldr x2, =__DATA_SIZE__ add x1, x1, :lo12:__DATA_ROM_START__
adrp x2, __DATA_RAM_END__
add x2, x2, :lo12:__DATA_RAM_END__
sub x2, x2, x0
bl memcpy bl memcpy
ldr x0, =__BSS_START__ adrp x0,__BSS_START__
add x0, x0, :lo12:__BSS_START__
mov x1, #0 mov x1, #0
ldr x2, =__BSS_SIZE__ adrp x2, __BSS_END__
add x2, x2, :lo12:__BSS_END__
sub x2, x2, x0
bl memset bl memset
ldp x29, x30, [sp], #16 ldp x29, x30, [sp], #16

3
lib/xlat_tables_v2/aarch64/enable_mmu.S
View File

@ -45,7 +45,8 @@
tlbi_invalidate_all \el tlbi_invalidate_all \el
mov x7, x0 mov x7, x0
ldr x0, =mmu_cfg_params adrp x0, mmu_cfg_params
add x0, x0, :lo12:mmu_cfg_params
/* MAIR */ /* MAIR */
ldr x1, [x0, #(MMU_CFG_MAIR << 3)] ldr x1, [x0, #(MMU_CFG_MAIR << 3)]