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intel: Add function to check fpga readiness 

Create a function to check for fpga readiness, and move the checking out
of bridge enable function.

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I3f473ffeffa9ce181a48977560c8bda19c6123c0
This commit is contained in:
Hadi Asyrafi 2019-12-24 14:43:22 +08:00 committed by Abdul Halim, Muhammad Hadi Asyrafi
parent 9c8f3af50a
commit f2decc7690
5 changed files with 28 additions and 23 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
plat/intel/soc/agilex/bl2_plat_setup.c
View File

@ -75,7 +75,9 @@ void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1,
init_ncore_ccu();
init_hard_memory_controller();
mailbox_init();
socfpga_bridges_enable();
if (!intel_mailbox_is_fpga_not_ready())
socfpga_bridges_enable();
}

1
plat/intel/soc/common/include/socfpga_mailbox.h
View File

@ -120,5 +120,6 @@ void mailbox_reset_cold(void);
void mailbox_clear_response(void);
uint32_t intel_mailbox_get_config_status(uint32_t cmd);
int intel_mailbox_is_fpga_not_ready(void);
#endif /* SOCFPGA_MBOX_H */

10
plat/intel/soc/common/soc/socfpga_mailbox.c
View File

@ -316,3 +316,13 @@ uint32_t intel_mailbox_get_config_status(uint32_t cmd)
return MBOX_CFGSTAT_STATE_CONFIG;
}
int intel_mailbox_is_fpga_not_ready(void)
{
int ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS);
if (ret && ret != MBOX_CFGSTAT_STATE_CONFIG)
ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS);
return ret;
}

32
plat/intel/soc/common/soc/socfpga_reset_manager.c
View File

@ -101,29 +101,19 @@ static int poll_idle_status(uint32_t addr, uint32_t mask, uint32_t match)
int socfpga_bridges_enable(void)
{
uint32_t status, poll_addr;
/* Clear idle request */
mmio_setbits_32(SOCFPGA_SYSMGR(NOC_IDLEREQ_CLR), ~0);
status = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS);
/* De-assert all bridges */
mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), ~0);
if (!status) {
/* Clear idle request */
mmio_setbits_32(SOCFPGA_SYSMGR(NOC_IDLEREQ_CLR), ~0);
/* De-assert all bridges */
mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), ~0);
/* Wait until idle ack becomes 0 */
poll_addr = SOCFPGA_SYSMGR(NOC_IDLEACK);
return poll_idle_status(poll_addr, IDLE_DATA_MASK, 0);
}
return status;
/* Wait until idle ack becomes 0 */
return poll_idle_status(SOCFPGA_SYSMGR(NOC_IDLEACK),
IDLE_DATA_MASK, 0);
}
int socfpga_bridges_disable(void)
{
uint32_t poll_addr;
/* Set idle request */
mmio_write_32(SOCFPGA_SYSMGR(NOC_IDLEREQ_SET), ~0);
@ -131,13 +121,13 @@ int socfpga_bridges_disable(void)
mmio_setbits_32(SOCFPGA_SYSMGR(NOC_TIMEOUT), 1);
/* Wait until each idle ack bit toggle to 1 */
poll_addr = SOCFPGA_SYSMGR(NOC_IDLEACK);
if (poll_idle_status(poll_addr, IDLE_DATA_MASK, IDLE_DATA_MASK))
if (poll_idle_status(SOCFPGA_SYSMGR(NOC_IDLEACK),
IDLE_DATA_MASK, IDLE_DATA_MASK))
return -ETIMEDOUT;
/* Wait until each idle status bit toggle to 1 */
poll_addr = SOCFPGA_SYSMGR(NOC_IDLESTATUS);
if (poll_idle_status(poll_addr, IDLE_DATA_MASK, IDLE_DATA_MASK))
if (poll_idle_status(SOCFPGA_SYSMGR(NOC_IDLESTATUS),
IDLE_DATA_MASK, IDLE_DATA_MASK))
return -ETIMEDOUT;
/* Assert all bridges */

4
plat/intel/soc/stratix10/bl2_plat_setup.c
View File

@ -73,7 +73,9 @@ void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1,
socfpga_delay_timer_init();
init_hard_memory_controller();
mailbox_init();
socfpga_bridges_enable();
if (!intel_mailbox_is_fpga_not_ready())
socfpga_bridges_enable();
}