Merge changes I072c0f61,I798401f4,I9648ef55,I7225d9fa,Ife682288, ... into integration
* changes: rcar_gen3: drivers: ddr_b: Update DDR setting for H3, M3, M3N rcar_gen3: drivers: qos: update QoS setting rcar_gen3: drivers: ddr_b: Fix checkpatch errors in headers rcar_gen3: drivers: ddr_b: Fix line-over-80s rcar_gen3: drivers: ddr_b: Further checkpatch cleanups rcar_gen3: drivers: ddr_b: Clean up camel case rcar_get3: drivers: ddr_b: Basic checkpatch fixes rcar_get3: drivers: ddr: Partly unify register macros between DDR A and B rcar_get3: drivers: ddr: Clean up common code
This commit is contained in:
commit
f38e5182f7
|
@ -12,7 +12,7 @@
|
|||
#include "../qos_reg.h"
|
||||
#include "qos_init_m3_v30.h"
|
||||
|
||||
#define RCAR_QOS_VERSION "rev.0.03"
|
||||
#define RCAR_QOS_VERSION "rev.0.04"
|
||||
|
||||
#define QOSWT_TIME_BANK0 20000000U /* unit:ns */
|
||||
|
||||
|
|
|
@ -32,8 +32,8 @@ static uint64_t mstat_fix[] = {
|
|||
/* 0x00c0, */ 0x000C04020000FFFFUL,
|
||||
/* 0x00c8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x00d0, */ 0x000C04010000FFFFUL,
|
||||
/* 0x00d8, */ 0x000C100D0000FFFFUL,
|
||||
/* 0x00e0, */ 0x000C1C1B0000FFFFUL,
|
||||
/* 0x00d8, */ 0x000C08050000FFFFUL,
|
||||
/* 0x00e0, */ 0x000C10100000FFFFUL,
|
||||
/* 0x00e8, */ 0x0000000000000000UL,
|
||||
/* 0x00f0, */ 0x001024090000FFFFUL,
|
||||
/* 0x00f8, */ 0x0000000000000000UL,
|
||||
|
@ -41,7 +41,7 @@ static uint64_t mstat_fix[] = {
|
|||
/* 0x0108, */ 0x0000000000000000UL,
|
||||
/* 0x0110, */ 0x00100C090000FFFFUL,
|
||||
/* 0x0118, */ 0x0000000000000000UL,
|
||||
/* 0x0120, */ 0x000C1C1B0000FFFFUL,
|
||||
/* 0x0120, */ 0x000C10100000FFFFUL,
|
||||
/* 0x0128, */ 0x0000000000000000UL,
|
||||
/* 0x0130, */ 0x0000000000000000UL,
|
||||
/* 0x0138, */ 0x00100C0B0000FFFFUL,
|
||||
|
|
|
@ -32,8 +32,8 @@ static uint64_t mstat_fix[] = {
|
|||
/* 0x00c0, */ 0x000C08040000FFFFUL,
|
||||
/* 0x00c8, */ 0x000C04020000FFFFUL,
|
||||
/* 0x00d0, */ 0x000C04020000FFFFUL,
|
||||
/* 0x00d8, */ 0x000C1C1A0000FFFFUL,
|
||||
/* 0x00e0, */ 0x000C38360000FFFFUL,
|
||||
/* 0x00d8, */ 0x000C0C0A0000FFFFUL,
|
||||
/* 0x00e0, */ 0x000C201F0000FFFFUL,
|
||||
/* 0x00e8, */ 0x0000000000000000UL,
|
||||
/* 0x00f0, */ 0x001044110000FFFFUL,
|
||||
/* 0x00f8, */ 0x0000000000000000UL,
|
||||
|
@ -41,7 +41,7 @@ static uint64_t mstat_fix[] = {
|
|||
/* 0x0108, */ 0x0000000000000000UL,
|
||||
/* 0x0110, */ 0x001014110000FFFFUL,
|
||||
/* 0x0118, */ 0x0000000000000000UL,
|
||||
/* 0x0120, */ 0x000C38360000FFFFUL,
|
||||
/* 0x0120, */ 0x000C201F0000FFFFUL,
|
||||
/* 0x0128, */ 0x0000000000000000UL,
|
||||
/* 0x0130, */ 0x0000000000000000UL,
|
||||
/* 0x0138, */ 0x001018150000FFFFUL,
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
|
||||
* Copyright (c) 2018-2019, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
@ -9,10 +9,10 @@
|
|||
|
||||
extern int32_t rcar_dram_init(void);
|
||||
|
||||
#define INITDRAM_OK (0)
|
||||
#define INITDRAM_NG (0xffffffff)
|
||||
#define INITDRAM_ERR_I (0xffffffff)
|
||||
#define INITDRAM_ERR_O (0xfffffffe)
|
||||
#define INITDRAM_ERR_T (0xfffffff0)
|
||||
#define INITDRAM_OK 0
|
||||
#define INITDRAM_NG 0xffffffff
|
||||
#define INITDRAM_ERR_I 0xffffffff
|
||||
#define INITDRAM_ERR_O 0xfffffffe
|
||||
#define INITDRAM_ERR_T 0xfffffff0
|
||||
|
||||
#endif /* BOOT_INIT_DRAM_H */
|
||||
|
|
|
@ -5,287 +5,4 @@
|
|||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef BOOT_INIT_DRAM_REGDEF_H_
|
||||
#define BOOT_INIT_DRAM_REGDEF_H_
|
||||
|
||||
/* DBSC registers */
|
||||
#define DBSC_DBSYSCONF0 0xE6790000U
|
||||
#define DBSC_DBSYSCONF1 0xE6790004U
|
||||
#define DBSC_DBPHYCONF0 0xE6790010U
|
||||
#define DBSC_DBKIND 0xE6790020U
|
||||
#define DBSC_DBMEMCONF00 0xE6790030U
|
||||
#define DBSC_DBMEMCONF01 0xE6790034U
|
||||
#define DBSC_DBMEMCONF02 0xE6790038U
|
||||
#define DBSC_DBMEMCONF03 0xE679003CU
|
||||
#define DBSC_DBMEMCONF10 0xE6790040U
|
||||
#define DBSC_DBMEMCONF11 0xE6790044U
|
||||
#define DBSC_DBMEMCONF12 0xE6790048U
|
||||
#define DBSC_DBMEMCONF13 0xE679004CU
|
||||
#define DBSC_DBMEMCONF20 0xE6790050U
|
||||
#define DBSC_DBMEMCONF21 0xE6790054U
|
||||
#define DBSC_DBMEMCONF22 0xE6790058U
|
||||
#define DBSC_DBMEMCONF23 0xE679005CU
|
||||
#define DBSC_DBMEMCONF30 0xE6790060U
|
||||
#define DBSC_DBMEMCONF31 0xE6790064U
|
||||
#define DBSC_DBMEMCONF32 0xE6790068U
|
||||
#define DBSC_DBMEMCONF33 0xE679006CU
|
||||
#define DBSC_DBSYSCNT0 0xE6790100U
|
||||
#define DBSC_DBSVCR1 0xE6790104U
|
||||
#define DBSC_DBSTATE0 0xE6790108U
|
||||
#define DBSC_DBSTATE1 0xE679010CU
|
||||
#define DBSC_DBINTEN 0xE6790180U
|
||||
#define DBSC_DBINTSTAT0 0xE6790184U
|
||||
#define DBSC_DBACEN 0xE6790200U
|
||||
#define DBSC_DBRFEN 0xE6790204U
|
||||
#define DBSC_DBCMD 0xE6790208U
|
||||
#define DBSC_DBWAIT 0xE6790210U
|
||||
#define DBSC_DBSYSCTRL0 0xE6790280U
|
||||
#define DBSC_DBTR0 0xE6790300U
|
||||
#define DBSC_DBTR1 0xE6790304U
|
||||
#define DBSC_DBTR2 0xE6790308U
|
||||
#define DBSC_DBTR3 0xE679030CU
|
||||
#define DBSC_DBTR4 0xE6790310U
|
||||
#define DBSC_DBTR5 0xE6790314U
|
||||
#define DBSC_DBTR6 0xE6790318U
|
||||
#define DBSC_DBTR7 0xE679031CU
|
||||
#define DBSC_DBTR8 0xE6790320U
|
||||
#define DBSC_DBTR9 0xE6790324U
|
||||
#define DBSC_DBTR10 0xE6790328U
|
||||
#define DBSC_DBTR11 0xE679032CU
|
||||
#define DBSC_DBTR12 0xE6790330U
|
||||
#define DBSC_DBTR13 0xE6790334U
|
||||
#define DBSC_DBTR14 0xE6790338U
|
||||
#define DBSC_DBTR15 0xE679033CU
|
||||
#define DBSC_DBTR16 0xE6790340U
|
||||
#define DBSC_DBTR17 0xE6790344U
|
||||
#define DBSC_DBTR18 0xE6790348U
|
||||
#define DBSC_DBTR19 0xE679034CU
|
||||
#define DBSC_DBTR20 0xE6790350U
|
||||
#define DBSC_DBTR21 0xE6790354U
|
||||
#define DBSC_DBTR22 0xE6790358U
|
||||
#define DBSC_DBTR23 0xE679035CU
|
||||
#define DBSC_DBTR24 0xE6790360U
|
||||
#define DBSC_DBTR25 0xE6790364U
|
||||
#define DBSC_DBBL 0xE6790400U
|
||||
#define DBSC_DBRFCNF1 0xE6790414U
|
||||
#define DBSC_DBRFCNF2 0xE6790418U
|
||||
#define DBSC_DBTSPCNF 0xE6790420U
|
||||
#define DBSC_DBCALCNF 0xE6790424U
|
||||
#define DBSC_DBRNK2 0xE6790438U
|
||||
#define DBSC_DBRNK3 0xE679043CU
|
||||
#define DBSC_DBRNK4 0xE6790440U
|
||||
#define DBSC_DBRNK5 0xE6790444U
|
||||
#define DBSC_DBPDNCNF 0xE6790450U
|
||||
#define DBSC_DBODT0 0xE6790460U
|
||||
#define DBSC_DBODT1 0xE6790464U
|
||||
#define DBSC_DBODT2 0xE6790468U
|
||||
#define DBSC_DBODT3 0xE679046CU
|
||||
#define DBSC_DBODT4 0xE6790470U
|
||||
#define DBSC_DBODT5 0xE6790474U
|
||||
#define DBSC_DBODT6 0xE6790478U
|
||||
#define DBSC_DBODT7 0xE679047CU
|
||||
#define DBSC_DBADJ0 0xE6790500U
|
||||
#define DBSC_DBDBICNT 0xE6790518U
|
||||
#define DBSC_DBDFIPMSTRCNF 0xE6790520U
|
||||
#define DBSC_DBDFIPMSTRSTAT 0xE6790524U
|
||||
#define DBSC_DBDFILPCNF 0xE6790528U
|
||||
#define DBSC_DBDFICUPDCNF 0xE679052CU
|
||||
#define DBSC_DBDFISTAT0 0xE6790600U
|
||||
#define DBSC_DBDFICNT0 0xE6790604U
|
||||
#define DBSC_DBPDCNT00 0xE6790610U
|
||||
#define DBSC_DBPDCNT01 0xE6790614U
|
||||
#define DBSC_DBPDCNT02 0xE6790618U
|
||||
#define DBSC_DBPDCNT03 0xE679061CU
|
||||
#define DBSC_DBPDLK0 0xE6790620U
|
||||
#define DBSC_DBPDRGA0 0xE6790624U
|
||||
#define DBSC_DBPDRGD0 0xE6790628U
|
||||
#define DBSC_DBPDSTAT00 0xE6790630U
|
||||
#define DBSC_DBDFISTAT1 0xE6790640U
|
||||
#define DBSC_DBDFICNT1 0xE6790644U
|
||||
#define DBSC_DBPDCNT10 0xE6790650U
|
||||
#define DBSC_DBPDCNT11 0xE6790654U
|
||||
#define DBSC_DBPDCNT12 0xE6790658U
|
||||
#define DBSC_DBPDCNT13 0xE679065CU
|
||||
#define DBSC_DBPDLK1 0xE6790660U
|
||||
#define DBSC_DBPDRGA1 0xE6790664U
|
||||
#define DBSC_DBPDRGD1 0xE6790668U
|
||||
#define DBSC_DBPDSTAT10 0xE6790670U
|
||||
#define DBSC_DBDFISTAT2 0xE6790680U
|
||||
#define DBSC_DBDFICNT2 0xE6790684U
|
||||
#define DBSC_DBPDCNT20 0xE6790690U
|
||||
#define DBSC_DBPDCNT21 0xE6790694U
|
||||
#define DBSC_DBPDCNT22 0xE6790698U
|
||||
#define DBSC_DBPDCNT23 0xE679069CU
|
||||
#define DBSC_DBPDLK2 0xE67906A0U
|
||||
#define DBSC_DBPDRGA2 0xE67906A4U
|
||||
#define DBSC_DBPDRGD2 0xE67906A8U
|
||||
#define DBSC_DBPDSTAT20 0xE67906B0U
|
||||
#define DBSC_DBDFISTAT3 0xE67906C0U
|
||||
#define DBSC_DBDFICNT3 0xE67906C4U
|
||||
#define DBSC_DBPDCNT30 0xE67906D0U
|
||||
#define DBSC_DBPDCNT31 0xE67906D4U
|
||||
#define DBSC_DBPDCNT32 0xE67906D8U
|
||||
#define DBSC_DBPDCNT33 0xE67906DCU
|
||||
#define DBSC_DBPDLK3 0xE67906E0U
|
||||
#define DBSC_DBPDRGA3 0xE67906E4U
|
||||
#define DBSC_DBPDRGD3 0xE67906E8U
|
||||
#define DBSC_DBPDSTAT30 0xE67906F0U
|
||||
#define DBSC_DBBUS0CNF0 0xE6790800U
|
||||
#define DBSC_DBBUS0CNF1 0xE6790804U
|
||||
#define DBSC_DBCAM0CNF1 0xE6790904U
|
||||
#define DBSC_DBCAM0CNF2 0xE6790908U
|
||||
#define DBSC_DBCAM0CNF3 0xE679090CU
|
||||
#define DBSC_DBCAM0CTRL0 0xE6790940U
|
||||
#define DBSC_DBCAM0STAT0 0xE6790980U
|
||||
#define DBSC_DBCAM1STAT0 0xE6790990U
|
||||
#define DBSC_DBBCAMSWAP 0xE67909F0U
|
||||
#define DBSC_DBBCAMDIS 0xE67909FCU
|
||||
#define DBSC_DBSCHCNT0 0xE6791000U
|
||||
#define DBSC_DBSCHCNT1 0xE6791004U
|
||||
#define DBSC_DBSCHSZ0 0xE6791010U
|
||||
#define DBSC_DBSCHRW0 0xE6791020U
|
||||
#define DBSC_DBSCHRW1 0xE6791024U
|
||||
#define DBSC_DBSCHQOS00 0xE6791030U
|
||||
#define DBSC_DBSCHQOS01 0xE6791034U
|
||||
#define DBSC_DBSCHQOS02 0xE6791038U
|
||||
#define DBSC_DBSCHQOS03 0xE679103CU
|
||||
#define DBSC_DBSCHQOS10 0xE6791040U
|
||||
#define DBSC_DBSCHQOS11 0xE6791044U
|
||||
#define DBSC_DBSCHQOS12 0xE6791048U
|
||||
#define DBSC_DBSCHQOS13 0xE679104CU
|
||||
#define DBSC_DBSCHQOS20 0xE6791050U
|
||||
#define DBSC_DBSCHQOS21 0xE6791054U
|
||||
#define DBSC_DBSCHQOS22 0xE6791058U
|
||||
#define DBSC_DBSCHQOS23 0xE679105CU
|
||||
#define DBSC_DBSCHQOS30 0xE6791060U
|
||||
#define DBSC_DBSCHQOS31 0xE6791064U
|
||||
#define DBSC_DBSCHQOS32 0xE6791068U
|
||||
#define DBSC_DBSCHQOS33 0xE679106CU
|
||||
#define DBSC_DBSCHQOS40 0xE6791070U
|
||||
#define DBSC_DBSCHQOS41 0xE6791074U
|
||||
#define DBSC_DBSCHQOS42 0xE6791078U
|
||||
#define DBSC_DBSCHQOS43 0xE679107CU
|
||||
#define DBSC_DBSCHQOS50 0xE6791080U
|
||||
#define DBSC_DBSCHQOS51 0xE6791084U
|
||||
#define DBSC_DBSCHQOS52 0xE6791088U
|
||||
#define DBSC_DBSCHQOS53 0xE679108CU
|
||||
#define DBSC_DBSCHQOS60 0xE6791090U
|
||||
#define DBSC_DBSCHQOS61 0xE6791094U
|
||||
#define DBSC_DBSCHQOS62 0xE6791098U
|
||||
#define DBSC_DBSCHQOS63 0xE679109CU
|
||||
#define DBSC_DBSCHQOS70 0xE67910A0U
|
||||
#define DBSC_DBSCHQOS71 0xE67910A4U
|
||||
#define DBSC_DBSCHQOS72 0xE67910A8U
|
||||
#define DBSC_DBSCHQOS73 0xE67910ACU
|
||||
#define DBSC_DBSCHQOS80 0xE67910B0U
|
||||
#define DBSC_DBSCHQOS81 0xE67910B4U
|
||||
#define DBSC_DBSCHQOS82 0xE67910B8U
|
||||
#define DBSC_DBSCHQOS83 0xE67910BCU
|
||||
#define DBSC_DBSCHQOS90 0xE67910C0U
|
||||
#define DBSC_DBSCHQOS91 0xE67910C4U
|
||||
#define DBSC_DBSCHQOS92 0xE67910C8U
|
||||
#define DBSC_DBSCHQOS93 0xE67910CCU
|
||||
#define DBSC_DBSCHQOS100 0xE67910D0U
|
||||
#define DBSC_DBSCHQOS101 0xE67910D4U
|
||||
#define DBSC_DBSCHQOS102 0xE67910D8U
|
||||
#define DBSC_DBSCHQOS103 0xE67910DCU
|
||||
#define DBSC_DBSCHQOS110 0xE67910E0U
|
||||
#define DBSC_DBSCHQOS111 0xE67910E4U
|
||||
#define DBSC_DBSCHQOS112 0xE67910E8U
|
||||
#define DBSC_DBSCHQOS113 0xE67910ECU
|
||||
#define DBSC_DBSCHQOS120 0xE67910F0U
|
||||
#define DBSC_DBSCHQOS121 0xE67910F4U
|
||||
#define DBSC_DBSCHQOS122 0xE67910F8U
|
||||
#define DBSC_DBSCHQOS123 0xE67910FCU
|
||||
#define DBSC_DBSCHQOS130 0xE6791100U
|
||||
#define DBSC_DBSCHQOS131 0xE6791104U
|
||||
#define DBSC_DBSCHQOS132 0xE6791108U
|
||||
#define DBSC_DBSCHQOS133 0xE679110CU
|
||||
#define DBSC_DBSCHQOS140 0xE6791110U
|
||||
#define DBSC_DBSCHQOS141 0xE6791114U
|
||||
#define DBSC_DBSCHQOS142 0xE6791118U
|
||||
#define DBSC_DBSCHQOS143 0xE679111CU
|
||||
#define DBSC_DBSCHQOS150 0xE6791120U
|
||||
#define DBSC_DBSCHQOS151 0xE6791124U
|
||||
#define DBSC_DBSCHQOS152 0xE6791128U
|
||||
#define DBSC_DBSCHQOS153 0xE679112CU
|
||||
#define DBSC_SCFCTST0 0xE6791700U
|
||||
#define DBSC_SCFCTST1 0xE6791708U
|
||||
#define DBSC_SCFCTST2 0xE679170CU
|
||||
#define DBSC_DBMRRDR0 0xE6791800U
|
||||
#define DBSC_DBMRRDR1 0xE6791804U
|
||||
#define DBSC_DBMRRDR2 0xE6791808U
|
||||
#define DBSC_DBMRRDR3 0xE679180CU
|
||||
#define DBSC_DBMRRDR4 0xE6791810U
|
||||
#define DBSC_DBMRRDR5 0xE6791814U
|
||||
#define DBSC_DBMRRDR6 0xE6791818U
|
||||
#define DBSC_DBMRRDR7 0xE679181CU
|
||||
#define DBSC_DBDTMP0 0xE6791820U
|
||||
#define DBSC_DBDTMP1 0xE6791824U
|
||||
#define DBSC_DBDTMP2 0xE6791828U
|
||||
#define DBSC_DBDTMP3 0xE679182CU
|
||||
#define DBSC_DBDTMP4 0xE6791830U
|
||||
#define DBSC_DBDTMP5 0xE6791834U
|
||||
#define DBSC_DBDTMP6 0xE6791838U
|
||||
#define DBSC_DBDTMP7 0xE679183CU
|
||||
#define DBSC_DBDQSOSC00 0xE6791840U
|
||||
#define DBSC_DBDQSOSC01 0xE6791844U
|
||||
#define DBSC_DBDQSOSC10 0xE6791848U
|
||||
#define DBSC_DBDQSOSC11 0xE679184CU
|
||||
#define DBSC_DBDQSOSC20 0xE6791850U
|
||||
#define DBSC_DBDQSOSC21 0xE6791854U
|
||||
#define DBSC_DBDQSOSC30 0xE6791858U
|
||||
#define DBSC_DBDQSOSC31 0xE679185CU
|
||||
#define DBSC_DBDQSOSC40 0xE6791860U
|
||||
#define DBSC_DBDQSOSC41 0xE6791864U
|
||||
#define DBSC_DBDQSOSC50 0xE6791868U
|
||||
#define DBSC_DBDQSOSC51 0xE679186CU
|
||||
#define DBSC_DBDQSOSC60 0xE6791870U
|
||||
#define DBSC_DBDQSOSC61 0xE6791874U
|
||||
#define DBSC_DBDQSOSC70 0xE6791878U
|
||||
#define DBSC_DBDQSOSC71 0xE679187CU
|
||||
#define DBSC_DBOSCTHH00 0xE6791880U
|
||||
#define DBSC_DBOSCTHH01 0xE6791884U
|
||||
#define DBSC_DBOSCTHH10 0xE6791888U
|
||||
#define DBSC_DBOSCTHH11 0xE679188CU
|
||||
#define DBSC_DBOSCTHH20 0xE6791890U
|
||||
#define DBSC_DBOSCTHH21 0xE6791894U
|
||||
#define DBSC_DBOSCTHH30 0xE6791898U
|
||||
#define DBSC_DBOSCTHH31 0xE679189CU
|
||||
#define DBSC_DBOSCTHH40 0xE67918A0U
|
||||
#define DBSC_DBOSCTHH41 0xE67918A4U
|
||||
#define DBSC_DBOSCTHH50 0xE67918A8U
|
||||
#define DBSC_DBOSCTHH51 0xE67918ACU
|
||||
#define DBSC_DBOSCTHH60 0xE67918B0U
|
||||
#define DBSC_DBOSCTHH61 0xE67918B4U
|
||||
#define DBSC_DBOSCTHH70 0xE67918B8U
|
||||
#define DBSC_DBOSCTHH71 0xE67918BCU
|
||||
#define DBSC_DBOSCTHL00 0xE67918C0U
|
||||
#define DBSC_DBOSCTHL01 0xE67918C4U
|
||||
#define DBSC_DBOSCTHL10 0xE67918C8U
|
||||
#define DBSC_DBOSCTHL11 0xE67918CCU
|
||||
#define DBSC_DBOSCTHL20 0xE67918D0U
|
||||
#define DBSC_DBOSCTHL21 0xE67918D4U
|
||||
#define DBSC_DBOSCTHL30 0xE67918D8U
|
||||
#define DBSC_DBOSCTHL31 0xE67918DCU
|
||||
#define DBSC_DBOSCTHL40 0xE67918E0U
|
||||
#define DBSC_DBOSCTHL41 0xE67918E4U
|
||||
#define DBSC_DBOSCTHL50 0xE67918E8U
|
||||
#define DBSC_DBOSCTHL51 0xE67918ECU
|
||||
#define DBSC_DBOSCTHL60 0xE67918F0U
|
||||
#define DBSC_DBOSCTHL61 0xE67918F4U
|
||||
#define DBSC_DBOSCTHL70 0xE67918F8U
|
||||
#define DBSC_DBOSCTHL71 0xE67918FCU
|
||||
#define DBSC_DBMEMSWAPCONF0 0xE6792000U
|
||||
|
||||
/* CPG registers */
|
||||
#define CPG_SRCR4 0xE61500BCU
|
||||
#define CPG_PLLECR 0xE61500D0U
|
||||
#define CPG_CPGWPR 0xE6150900U
|
||||
#define CPG_CPGWPCR 0xE6150904U
|
||||
#define CPG_SRSTCLR4 0xE6150950U
|
||||
|
||||
/* MODE Monitor registers */
|
||||
#define RST_MODEMR 0xE6160060U
|
||||
|
||||
#endif /* BOOT_INIT_DRAM_REGDEF_H_*/
|
||||
#include "../ddr_regs.h"
|
||||
|
|
|
@ -8,8 +8,8 @@
|
|||
#include <stdint.h>
|
||||
#include <lib/mmio.h>
|
||||
#include <common/debug.h>
|
||||
|
||||
#include "boot_init_dram_regdef.h"
|
||||
#include "rcar_def.h"
|
||||
#include "../ddr_regs.h"
|
||||
|
||||
#define RCAR_DDR_VERSION "rev.0.01"
|
||||
|
||||
|
@ -23,7 +23,7 @@ static void init_ddr_d3_1866(void)
|
|||
|
||||
mmio_write_32(DBSC_DBSYSCNT0, 0x00001234);
|
||||
mmio_write_32(DBSC_DBKIND, 0x00000007);
|
||||
mmio_write_32(DBSC_DBMEMCONF00, 0x0f030a01);
|
||||
mmio_write_32(DBSC_DBMEMCONF_0_0, 0x0f030a01);
|
||||
mmio_write_32(DBSC_DBPHYCONF0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBTR0, 0x0000000D);
|
||||
mmio_write_32(DBSC_DBTR1, 0x00000009);
|
||||
|
@ -51,249 +51,249 @@ static void init_ddr_d3_1866(void)
|
|||
mmio_write_32(DBSC_DBODT0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBADJ0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBSYSCONF1, 0x00000002);
|
||||
mmio_write_32(DBSC_DBDFICNT0, 0x00000010);
|
||||
mmio_write_32(DBSC_DBDFICNT_0, 0x00000010);
|
||||
mmio_write_32(DBSC_DBBCAMDIS, 0x00000001);
|
||||
mmio_write_32(DBSC_DBSCHRW1, 0x00000046);
|
||||
mmio_write_32(DBSC_SCFCTST0, 0x0D020D04);
|
||||
mmio_write_32(DBSC_SCFCTST1, 0x0306040C);
|
||||
|
||||
mmio_write_32(DBSC_DBPDLK0, 0x0000A55A);
|
||||
mmio_write_32(DBSC_DBPDLK_0, 0x0000A55A);
|
||||
mmio_write_32(DBSC_DBCMD, 0x01000001);
|
||||
mmio_write_32(DBSC_DBCMD, 0x08000000);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x80010000);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x80010000);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
|
||||
;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000008);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x000B8000);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x04058A04);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000091);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000095);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0007BBAD);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000099);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x04058A00);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000021);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0024641E);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x00010073);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000008);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x000B8000);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000090);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x04058A04);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000091);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000095);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0007BBAD);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000099);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000090);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x04058A00);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000021);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0024641E);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x00010073);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
|
||||
;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0C058A00);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x04058A00);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000090);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0C058A00);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000090);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x04058A00);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
|
||||
;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000003);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0780C700);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000007);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(30)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000003);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0780C700);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000007);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(30)))
|
||||
;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000004);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0A206F89);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000022);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x1000040B);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000023);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x35A00D77);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000024);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x2A8A2C28);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000025);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x30005E00);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000026);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0014CB49);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000027);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x00000F14);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000028);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x00000046);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000029);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x000000A0);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x0000002C);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x81003047);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000020);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x00181884);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x0000001A);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x33C03C10);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000004);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0A206F89);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000022);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x1000040B);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000023);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x35A00D77);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000024);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x2A8A2C28);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000025);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x30005E00);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000026);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0014CB49);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000027);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x00000F14);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000028);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x00000046);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000029);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x000000A0);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x81003047);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000020);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x00181884);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x0000001A);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x33C03C10);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
|
||||
;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000A7);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000A8);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000A9);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000C7);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000C8);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000C9);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000A7);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000A8);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000A9);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000C7);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000C8);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000C9);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D);
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x0000000E);
|
||||
r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0x0000FF00) >> 0x9;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x0000000E);
|
||||
r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0x0000FF00) >> 0x9;
|
||||
r3 = (r2 << 16) + (r2 << 8) + r2;
|
||||
r6 = (r2 << 24) + (r2 << 16) + (r2 << 8) + r2;
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000011);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r3);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000012);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r3);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000016);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r6);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000017);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r6);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000018);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r6);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000019);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r6);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000011);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r3);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000012);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r3);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000016);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r6);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000017);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r6);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000018);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r6);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000019);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r6);
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x00010181);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x00010181);
|
||||
mmio_write_32(DBSC_DBCMD, 0x08000001);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
|
||||
;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x00010601);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x00010601);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
|
||||
;
|
||||
|
||||
for (i = 0; i < 2; i++) {
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20);
|
||||
r5 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 0x8;
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20);
|
||||
r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF;
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20);
|
||||
r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20);
|
||||
r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20);
|
||||
r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20);
|
||||
r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7;
|
||||
|
||||
if (r6 > 0) {
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r2 | ((r7 + 0x1) & 0x7));
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r2 | r6);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r7 + 0x1) & 0x7));
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r2 | r6);
|
||||
} else {
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r2 | r7);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r2 | r7);
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r2 |
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r2 |
|
||||
((r6 + (r5 << 1)) & 0xFF));
|
||||
}
|
||||
}
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000005);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00C0);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x00010801);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000005);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00C0);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x00010801);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
|
||||
;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000005);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00D8);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0001F001);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000005);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00D8);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0001F001);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
|
||||
;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000AF);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD0);
|
||||
mmio_write_32(DBSC_DBPDRGD0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00));
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000CF);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD0);
|
||||
mmio_write_32(DBSC_DBPDRGD0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00));
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000AF);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD_0);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00));
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000CF);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD_0);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00));
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x0000002C);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x81003087);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x00010401);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x81003087);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x00010401);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
|
||||
;
|
||||
|
||||
for (i = 0; i < 2; i++) {
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20);
|
||||
r5 = ((mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 0x8);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20);
|
||||
r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20);
|
||||
r5 = ((mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20);
|
||||
r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20);
|
||||
r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20);
|
||||
r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7;
|
||||
r12 = (r5 >> 0x2);
|
||||
|
||||
if (r12 < r6) {
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r2 | ((r7 + 0x1) & 0x7));
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r7 + 0x1) & 0x7));
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r2 | ((r6 - r12) & 0xFF));
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r6 - r12) & 0xFF));
|
||||
} else {
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r2 | (r7 & 0x7));
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r2 |
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r2 | (r7 & 0x7));
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r2 |
|
||||
((r6 + r5 +
|
||||
(r5 >> 1) + r12) & 0xFF));
|
||||
}
|
||||
}
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x00015001);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x00015001);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
|
||||
;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000003);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0380C700);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000007);
|
||||
while (mmio_read_32(DBSC_DBPDRGD0) & BIT(30))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000003);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0380C700);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000007);
|
||||
while (mmio_read_32(DBSC_DBPDRGD_0) & BIT(30))
|
||||
;
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000021);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0024643E);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000021);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0024643E);
|
||||
|
||||
mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010);
|
||||
mmio_write_32(DBSC_DBCALCNF, 0x0100401B);
|
||||
|
@ -302,7 +302,7 @@ static void init_ddr_d3_1866(void)
|
|||
mmio_write_32(DBSC_DBDFICUPDCNF, 0x40100001);
|
||||
mmio_write_32(DBSC_DBRFEN, 0x00000001);
|
||||
mmio_write_32(DBSC_DBACEN, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDLK0, 0x00000000);
|
||||
mmio_write_32(DBSC_DBPDLK_0, 0x00000000);
|
||||
mmio_write_32(DBSC_DBSYSCNT0, 0x00000000);
|
||||
|
||||
#ifdef ddr_qos_init_setting // only for non qos_init
|
||||
|
@ -348,7 +348,7 @@ static void init_ddr_d3_1600(void)
|
|||
|
||||
mmio_write_32(DBSC_DBSYSCNT0, 0x00001234);
|
||||
mmio_write_32(DBSC_DBKIND, 0x00000007);
|
||||
mmio_write_32(DBSC_DBMEMCONF00, 0x0f030a01);
|
||||
mmio_write_32(DBSC_DBMEMCONF_0_0, 0x0f030a01);
|
||||
mmio_write_32(DBSC_DBPHYCONF0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBTR0, 0x0000000B);
|
||||
mmio_write_32(DBSC_DBTR1, 0x00000008);
|
||||
|
@ -376,248 +376,248 @@ static void init_ddr_d3_1600(void)
|
|||
mmio_write_32(DBSC_DBODT0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBADJ0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBSYSCONF1, 0x00000002);
|
||||
mmio_write_32(DBSC_DBDFICNT0, 0x00000010);
|
||||
mmio_write_32(DBSC_DBDFICNT_0, 0x00000010);
|
||||
mmio_write_32(DBSC_DBBCAMDIS, 0x00000001);
|
||||
mmio_write_32(DBSC_DBSCHRW1, 0x00000046);
|
||||
mmio_write_32(DBSC_SCFCTST0, 0x0D020C04);
|
||||
mmio_write_32(DBSC_SCFCTST1, 0x0305040C);
|
||||
|
||||
mmio_write_32(DBSC_DBPDLK0, 0x0000A55A);
|
||||
mmio_write_32(DBSC_DBPDLK_0, 0x0000A55A);
|
||||
mmio_write_32(DBSC_DBCMD, 0x01000001);
|
||||
mmio_write_32(DBSC_DBCMD, 0x08000000);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x80010000);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x80010000);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
|
||||
;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000008);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x000B8000);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x04058904);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000091);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000095);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0007BBAD);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000099);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x04058900);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000021);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0024641E);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x00010073);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000008);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x000B8000);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000090);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x04058904);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000091);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000095);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0007BBAD);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000099);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000090);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x04058900);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000021);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0024641E);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x00010073);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
|
||||
;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0C058900);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x04058900);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000090);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0C058900);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000090);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x04058900);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
|
||||
;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000003);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0780C700);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000007);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(30)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000003);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0780C700);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000007);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(30)))
|
||||
;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000004);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x08C05FF0);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000022);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x1000040B);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000023);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x2D9C0B66);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000024);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x2A88C400);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000025);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x30005200);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000026);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0014A9C9);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000027);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x00000D70);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000028);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x00000046);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000029);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x00000098);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x0000002C);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x81003047);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000020);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x00181884);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x0000001A);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x33C03C10);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000004);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x08C05FF0);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000022);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x1000040B);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000023);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x2D9C0B66);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000024);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x2A88C400);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000025);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x30005200);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000026);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0014A9C9);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000027);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x00000D70);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000028);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x00000046);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000029);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x00000098);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x81003047);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000020);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x00181884);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x0000001A);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x33C03C10);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
|
||||
;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000A7);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000A8);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000A9);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000C7);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000C8);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000C9);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000A7);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000A8);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000A9);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000C7);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000C8);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000C9);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D);
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x0000000E);
|
||||
r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0x0000FF00) >> 0x9;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x0000000E);
|
||||
r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0x0000FF00) >> 0x9;
|
||||
r3 = (r2 << 16) + (r2 << 8) + r2;
|
||||
r6 = (r2 << 24) + (r2 << 16) + (r2 << 8) + r2;
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000011);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r3);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000012);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r3);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000016);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r6);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000017);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r6);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000018);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r6);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000019);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r6);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000011);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r3);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000012);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r3);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000016);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r6);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000017);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r6);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000018);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r6);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000019);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r6);
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x00010181);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x00010181);
|
||||
mmio_write_32(DBSC_DBCMD, 0x08000001);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
|
||||
;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x00010601);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x00010601);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
|
||||
;
|
||||
|
||||
for (i = 0; i < 2; i++) {
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20);
|
||||
r5 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 0x8;
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20);
|
||||
r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF;
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20);
|
||||
r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20);
|
||||
r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20);
|
||||
r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20);
|
||||
r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7;
|
||||
if (r6 > 0) {
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r2 | ((r7 + 0x1) & 0x7));
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r2 | r6);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r7 + 0x1) & 0x7));
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r2 | r6);
|
||||
} else {
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r2 | r7);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r2 | r7);
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r2 |
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r2 |
|
||||
((r6 + (r5 << 1)) & 0xFF));
|
||||
}
|
||||
}
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000005);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00C0);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x00010801);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000005);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00C0);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x00010801);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
|
||||
;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000005);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00D8);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0001F001);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000005);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00D8);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0001F001);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
|
||||
;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000AF);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD0);
|
||||
mmio_write_32(DBSC_DBPDRGD0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00));
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000CF);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD0);
|
||||
mmio_write_32(DBSC_DBPDRGD0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00));
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000AF);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD_0);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00));
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000CF);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD_0);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00));
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x0000002C);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x81003087);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x00010401);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x81003087);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x00010401);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
|
||||
;
|
||||
|
||||
for (i = 0; i < 2; i++) {
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20);
|
||||
r5 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 0x8;
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20);
|
||||
r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20);
|
||||
r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20);
|
||||
r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20);
|
||||
r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20);
|
||||
r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7;
|
||||
r12 = (r5 >> 0x2);
|
||||
|
||||
if (r12 < r6) {
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r2 | ((r7 + 0x1) & 0x7));
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r7 + 0x1) & 0x7));
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r2 | ((r6 - r12) & 0xFF));
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r6 - r12) & 0xFF));
|
||||
} else {
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r2 | (r7 & 0x7));
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r2 |
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r2 | (r7 & 0x7));
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r2 |
|
||||
((r6 + r5 +
|
||||
(r5 >> 1) + r12) & 0xFF));
|
||||
}
|
||||
}
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x00015001);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x00015001);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
|
||||
;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000003);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0380C700);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000007);
|
||||
while (mmio_read_32(DBSC_DBPDRGD0) & BIT(30))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000003);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0380C700);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000007);
|
||||
while (mmio_read_32(DBSC_DBPDRGD_0) & BIT(30))
|
||||
;
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000021);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0024643E);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000021);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0024643E);
|
||||
|
||||
mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010);
|
||||
mmio_write_32(DBSC_DBCALCNF, 0x0100401B);
|
||||
|
@ -626,7 +626,7 @@ static void init_ddr_d3_1600(void)
|
|||
mmio_write_32(DBSC_DBDFICUPDCNF, 0x40100001);
|
||||
mmio_write_32(DBSC_DBRFEN, 0x00000001);
|
||||
mmio_write_32(DBSC_DBACEN, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDLK0, 0x00000000);
|
||||
mmio_write_32(DBSC_DBPDLK_0, 0x00000000);
|
||||
mmio_write_32(DBSC_DBSYSCNT0, 0x00000000);
|
||||
|
||||
#ifdef ddr_qos_init_setting // only for non qos_init
|
||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -9,7 +9,8 @@
|
|||
#include <lib/utils_def.h>
|
||||
#include <stdint.h>
|
||||
#include "boot_init_dram.h"
|
||||
#include "boot_init_dram_regdef.h"
|
||||
#include "rcar_def.h"
|
||||
#include "../ddr_regs.h"
|
||||
|
||||
static uint32_t init_ddr_v3m_1600(void)
|
||||
{
|
||||
|
@ -18,9 +19,9 @@ static uint32_t init_ddr_v3m_1600(void)
|
|||
mmio_write_32(DBSC_DBSYSCNT0, 0x00001234);
|
||||
mmio_write_32(DBSC_DBKIND, 0x00000007);
|
||||
#if RCAR_DRAM_DDR3L_MEMCONF == 0
|
||||
mmio_write_32(DBSC_DBMEMCONF00, 0x0f030a02); // 1GB: Eagle
|
||||
mmio_write_32(DBSC_DBMEMCONF_0_0, 0x0f030a02); // 1GB: Eagle
|
||||
#else
|
||||
mmio_write_32(DBSC_DBMEMCONF00, 0x10030a02); // 2GB: V3MSK
|
||||
mmio_write_32(DBSC_DBMEMCONF_0_0, 0x10030a02); // 2GB: V3MSK
|
||||
#endif
|
||||
mmio_write_32(DBSC_DBPHYCONF0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBTR0, 0x0000000B);
|
||||
|
@ -79,243 +80,243 @@ static uint32_t init_ddr_v3m_1600(void)
|
|||
mmio_write_32(DBSC_DBCAM0CNF2, 0x000001c4);
|
||||
mmio_write_32(DBSC_DBSCHSZ0, 0x00000003);
|
||||
mmio_write_32(DBSC_DBSCHRW1, 0x001a0080);
|
||||
mmio_write_32(DBSC_DBDFICNT0, 0x00000010);
|
||||
mmio_write_32(DBSC_DBDFICNT_0, 0x00000010);
|
||||
|
||||
mmio_write_32(DBSC_DBPDLK0, 0x0000A55A);
|
||||
mmio_write_32(DBSC_DBPDLK_0, 0x0000A55A);
|
||||
mmio_write_32(DBSC_DBCMD, 0x01000001);
|
||||
mmio_write_32(DBSC_DBCMD, 0x08000000);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x80010000);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x80010000);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
|
||||
;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000008);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x000B8000);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x04058904);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000091);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6D);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000095);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000099);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6D);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x04058900);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000021);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0024641E);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x00010073);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000008);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x000B8000);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000090);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x04058904);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000091);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6D);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000095);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000099);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6D);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000090);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x04058900);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000021);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0024641E);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x00010073);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
|
||||
;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0C058900);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x04058900);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000090);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0C058900);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000090);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x04058900);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
|
||||
;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000003);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0780C700);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000007);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(30)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000003);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0780C700);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000007);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(30)))
|
||||
;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000004);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x08C0C170);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000022);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x1000040B);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000023);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x2D9C0B66);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000024);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x2A88C400);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000025);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x30005200);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000026);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0014A9C9);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000027);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x00000D70);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000028);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x00000004);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000029);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x00000018);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x0000002C);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x81003047);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000020);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x00181884);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x0000001A);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x13C03C10);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000004);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x08C0C170);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000022);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x1000040B);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000023);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x2D9C0B66);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000024);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x2A88C400);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000025);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x30005200);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000026);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0014A9C9);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000027);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x00000D70);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000028);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x00000004);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000029);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x00000018);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x81003047);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000020);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x00181884);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x0000001A);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x13C03C10);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
|
||||
;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000A7);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000A8);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000A9);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000C7);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000C8);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000C9);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000E7);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000E8);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000E9);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000107);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000108);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000109);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x00010181);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000A7);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000A8);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000A9);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000C7);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000C8);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000C9);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000E7);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000E8);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000E9);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000107);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000108);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000109);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x00010181);
|
||||
mmio_write_32(DBSC_DBCMD, 0x08000001);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
|
||||
;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x00010601);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x00010601);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
|
||||
;
|
||||
|
||||
for (i = 0; i < 4; i++) {
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20);
|
||||
r5 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 8;
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20);
|
||||
r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF;
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20);
|
||||
r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20);
|
||||
r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 8;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20);
|
||||
r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20);
|
||||
r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7;
|
||||
|
||||
if (r6 > 0) {
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
|
||||
r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
|
||||
r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8);
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD0, ((r7 + 1) & 0x7) | r2);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
|
||||
r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r2 | r6);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, ((r7 + 1) & 0x7) | r2);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
|
||||
r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r2 | r6);
|
||||
} else {
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
|
||||
r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r2 | r7);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
|
||||
r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r2 | r7);
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
|
||||
r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r2 |
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
|
||||
r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r2 |
|
||||
(((r5 << 1) + r6) & 0xFF));
|
||||
}
|
||||
}
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000005);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00A0);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000E0);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000100);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x00010801);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000005);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00A0);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000100);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x00010801);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
|
||||
;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000005);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00B8);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0001F001);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000005);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00B8);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0001F001);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
|
||||
;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000E0);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000100);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x0000002C);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x81003087);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x00010401);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000100);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x81003087);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x00010401);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
|
||||
;
|
||||
|
||||
for (i = 0; i < 4; i++) {
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20);
|
||||
r5 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 8;
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20);
|
||||
r6 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20);
|
||||
r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 8;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20);
|
||||
r6 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF);
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20);
|
||||
r7 = (mmio_read_32(DBSC_DBPDRGD0) & 0x7);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20);
|
||||
r7 = (mmio_read_32(DBSC_DBPDRGD_0) & 0x7);
|
||||
r12 = (r5 >> 2);
|
||||
if (r6 - r12 > 0) {
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
|
||||
r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
|
||||
r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8);
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD0, ((r7 + 1) & 0x7) | r2);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
|
||||
r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, ((r7 + 1) & 0x7) | r2);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
|
||||
r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00);
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD0, ((r6 - r12) & 0xFF) | r2);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, ((r6 - r12) & 0xFF) | r2);
|
||||
} else {
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
|
||||
r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD0, (r7 & 0x7) | r2);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
|
||||
r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r2 |
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
|
||||
r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, (r7 & 0x7) | r2);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
|
||||
r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r2 |
|
||||
((r6 + r5 +
|
||||
(r5 >> 1) + r12) & 0xFF));
|
||||
}
|
||||
}
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000E0);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000100);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x00015001);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000100);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x00015001);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
|
||||
;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000003);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0380C700);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000007);
|
||||
while (mmio_read_32(DBSC_DBPDRGD0) & BIT(30))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000003);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0380C700);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000007);
|
||||
while (mmio_read_32(DBSC_DBPDRGD_0) & BIT(30))
|
||||
;
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000021);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0024643E);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000021);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0024643E);
|
||||
|
||||
mmio_write_32(DBSC_DBBUS0CNF1, 0x00000000);
|
||||
mmio_write_32(DBSC_DBBUS0CNF0, 0x00010001);
|
||||
|
@ -325,7 +326,7 @@ static uint32_t init_ddr_v3m_1600(void)
|
|||
mmio_write_32(DBSC_DBDFICUPDCNF, 0x40100001);
|
||||
mmio_write_32(DBSC_DBRFEN, 0x00000001);
|
||||
mmio_write_32(DBSC_DBACEN, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDLK0, 0x00000000);
|
||||
mmio_write_32(DBSC_DBPDLK_0, 0x00000000);
|
||||
mmio_write_32(0xE67F0024, 0x00000001);
|
||||
mmio_write_32(DBSC_DBSYSCNT0, 0x00000000);
|
||||
|
||||
|
|
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
@ -1,13 +1,14 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
|
||||
* Copyright (c) 2015-2019, Renesas Electronics Corporation.
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#define RCAR_DDR_VERSION "rev.0.36"
|
||||
#define DRAM_CH_CNT (0x04)
|
||||
#define SLICE_CNT (0x04)
|
||||
#define CS_CNT (0x02)
|
||||
#define RCAR_DDR_VERSION "rev.0.37"
|
||||
#define DRAM_CH_CNT 0x04
|
||||
#define SLICE_CNT 0x04
|
||||
#define CS_CNT 0x02
|
||||
|
||||
/* order : CS0A, CS0B, CS1A, CS1B */
|
||||
#define CSAB_CNT (CS_CNT * 2)
|
||||
|
@ -16,15 +17,16 @@
|
|||
#define CHAB_CNT (DRAM_CH_CNT * 2)
|
||||
|
||||
/* pll setting */
|
||||
#define CLK_DIV(a, diva, b, divb) (((a) * (divb)) /((b) * (diva)))
|
||||
#define CLK_DIV(a, diva, b, divb) (((a) * (divb)) / ((b) * (diva)))
|
||||
#define CLK_MUL(a, diva, b, divb) (((a) * (b)) / ((diva) * (divb)))
|
||||
|
||||
/* for ddr deisity setting */
|
||||
#define DBMEMCONF_REG(d3, row, bank, col, dw) \
|
||||
#define DBMEMCONF_REG(d3, row, bank, col, dw) \
|
||||
((d3) << 30 | ((row) << 24) | ((bank) << 16) | ((col) << 8) | (dw))
|
||||
|
||||
#define DBMEMCONF_REGD(density) \
|
||||
(DBMEMCONF_REG((density) % 2, ((density) + 1) / 2 + (29-3-10-2), 3, 10, 2))
|
||||
#define DBMEMCONF_REGD(density) \
|
||||
(DBMEMCONF_REG((density) % 2, ((density) + 1) / \
|
||||
2 + (29 - 3 - 10 - 2), 3, 10, 2))
|
||||
|
||||
#define DBMEMCONF_VAL(ch, cs) (DBMEMCONF_REGD(DBMEMCONF_DENS(ch, cs)))
|
||||
|
||||
|
@ -32,7 +34,6 @@
|
|||
#define DBSC_REFINTS (0x0)
|
||||
|
||||
/* system registers */
|
||||
#define CPG_BASE (0xE6150000U)
|
||||
#define CPG_FRQCRB (CPG_BASE + 0x0004U)
|
||||
|
||||
#define CPG_PLLECR (CPG_BASE + 0x00D0U)
|
||||
|
@ -45,10 +46,10 @@
|
|||
#define CPG_CPGWPR (CPG_BASE + 0x0900U)
|
||||
#define CPG_SRSTCLR4 (CPG_BASE + 0x0950U)
|
||||
|
||||
#define CPG_FRQCRB_KICK_BIT (1U<<31)
|
||||
#define CPG_PLLECR_PLL3E_BIT (1U<<3)
|
||||
#define CPG_PLLECR_PLL3ST_BIT (1U<<11)
|
||||
#define CPG_ZB3CKCR_ZB3ST_BIT (1U<<11)
|
||||
#define CPG_FRQCRB_KICK_BIT BIT(31)
|
||||
#define CPG_PLLECR_PLL3E_BIT BIT(3)
|
||||
#define CPG_PLLECR_PLL3ST_BIT BIT(11)
|
||||
#define CPG_ZB3CKCR_ZB3ST_BIT BIT(11)
|
||||
|
||||
#define RST_BASE (0xE6160000U)
|
||||
#define RST_MODEMR (RST_BASE + 0x0060U)
|
||||
|
@ -56,179 +57,7 @@
|
|||
#define LIFEC_CHIPID(x) (0xE6110040U + 0x04U * (x))
|
||||
|
||||
/* DBSC registers */
|
||||
#define DBSC_DBSYSCONF1 0xE6790004U
|
||||
#define DBSC_DBPHYCONF0 0xE6790010U
|
||||
#define DBSC_DBKIND 0xE6790020U
|
||||
|
||||
#define DBSC_DBMEMCONF(ch, cs) (0xE6790030U + 0x10U * (ch) + 0x04U * (cs))
|
||||
#define DBSC_DBMEMCONF_0_0 0xE6790030U
|
||||
#define DBSC_DBMEMCONF_0_1 0xE6790034U
|
||||
#define DBSC_DBMEMCONF_0_2 0xE6790038U
|
||||
#define DBSC_DBMEMCONF_0_3 0xE679003CU
|
||||
#define DBSC_DBMEMCONF_1_2 0xE6790048U
|
||||
#define DBSC_DBMEMCONF_1_3 0xE679004CU
|
||||
#define DBSC_DBMEMCONF_1_0 0xE6790040U
|
||||
#define DBSC_DBMEMCONF_1_1 0xE6790044U
|
||||
#define DBSC_DBMEMCONF_2_0 0xE6790050U
|
||||
#define DBSC_DBMEMCONF_2_1 0xE6790054U
|
||||
#define DBSC_DBMEMCONF_2_2 0xE6790058U
|
||||
#define DBSC_DBMEMCONF_2_3 0xE679005CU
|
||||
#define DBSC_DBMEMCONF_3_0 0xE6790060U
|
||||
#define DBSC_DBMEMCONF_3_1 0xE6790064U
|
||||
#define DBSC_DBMEMCONF_3_2 0xE6790068U
|
||||
#define DBSC_DBMEMCONF_3_3 0xE679006CU
|
||||
|
||||
#define DBSC_DBSYSCNT0 0xE6790100U
|
||||
|
||||
#define DBSC_DBACEN 0xE6790200U
|
||||
#define DBSC_DBRFEN 0xE6790204U
|
||||
#define DBSC_DBCMD 0xE6790208U
|
||||
#define DBSC_DBWAIT 0xE6790210U
|
||||
#define DBSC_DBSYSCTRL0 0xE6790280U
|
||||
|
||||
#define DBSC_DBTR(x) (0xE6790300U + 0x04U * (x))
|
||||
#define DBSC_DBTR0 0xE6790300U
|
||||
#define DBSC_DBTR1 0xE6790304U
|
||||
#define DBSC_DBTR3 0xE679030CU
|
||||
#define DBSC_DBTR4 0xE6790310U
|
||||
#define DBSC_DBTR5 0xE6790314U
|
||||
#define DBSC_DBTR6 0xE6790318U
|
||||
#define DBSC_DBTR7 0xE679031CU
|
||||
#define DBSC_DBTR8 0xE6790320U
|
||||
#define DBSC_DBTR9 0xE6790324U
|
||||
#define DBSC_DBTR10 0xE6790328U
|
||||
#define DBSC_DBTR11 0xE679032CU
|
||||
#define DBSC_DBTR12 0xE6790330U
|
||||
#define DBSC_DBTR13 0xE6790334U
|
||||
#define DBSC_DBTR14 0xE6790338U
|
||||
#define DBSC_DBTR15 0xE679033CU
|
||||
#define DBSC_DBTR16 0xE6790340U
|
||||
#define DBSC_DBTR17 0xE6790344U
|
||||
#define DBSC_DBTR18 0xE6790348U
|
||||
#define DBSC_DBTR19 0xE679034CU
|
||||
#define DBSC_DBTR20 0xE6790350U
|
||||
#define DBSC_DBTR21 0xE6790354U
|
||||
#define DBSC_DBTR22 0xE6790358U
|
||||
#define DBSC_DBTR23 0xE679035CU
|
||||
#define DBSC_DBTR24 0xE6790360U
|
||||
#define DBSC_DBTR25 0xE6790364U
|
||||
#define DBSC_DBTR26 0xE6790368U
|
||||
|
||||
#define DBSC_DBBL 0xE6790400U
|
||||
#define DBSC_DBRFCNF1 0xE6790414U
|
||||
#define DBSC_DBRFCNF2 0xE6790418U
|
||||
#define DBSC_DBTSPCNF 0xE6790420U
|
||||
#define DBSC_DBCALCNF 0xE6790424U
|
||||
#define DBSC_DBRNK(x) (0xE6790430U + 0x04U * (x))
|
||||
#define DBSC_DBRNK2 0xE6790438U
|
||||
#define DBSC_DBRNK3 0xE679043CU
|
||||
#define DBSC_DBRNK4 0xE6790440U
|
||||
#define DBSC_DBRNK5 0xE6790444U
|
||||
#define DBSC_DBODT(x) (0xE6790460U + 0x04U * (x))
|
||||
|
||||
#define DBSC_DBADJ0 0xE6790500U
|
||||
#define DBSC_DBDBICNT 0xE6790518U
|
||||
#define DBSC_DBDFIPMSTRCNF 0xE6790520U
|
||||
#define DBSC_DBDFICUPDCNF 0xE679052CU
|
||||
|
||||
#define DBSC_DBDFISTAT(ch) (0xE6790600U + 0x40U * (ch))
|
||||
#define DBSC_DBDFISTAT_0 0xE6790600U
|
||||
#define DBSC_DBDFISTAT_1 0xE6790640U
|
||||
#define DBSC_DBDFISTAT_2 0xE6790680U
|
||||
#define DBSC_DBDFISTAT_3 0xE67906C0U
|
||||
|
||||
#define DBSC_DBDFICNT(ch) (0xE6790604U + 0x40U * (ch))
|
||||
#define DBSC_DBDFICNT_0 0xE6790604U
|
||||
#define DBSC_DBDFICNT_1 0xE6790644U
|
||||
#define DBSC_DBDFICNT_2 0xE6790684U
|
||||
#define DBSC_DBDFICNT_3 0xE67906C4U
|
||||
|
||||
#define DBSC_DBPDCNT0(ch) (0xE6790610U + 0x40U * (ch))
|
||||
#define DBSC_DBPDCNT0_0 0xE6790610U
|
||||
#define DBSC_DBPDCNT0_1 0xE6790650U
|
||||
#define DBSC_DBPDCNT0_2 0xE6790690U
|
||||
#define DBSC_DBPDCNT0_3 0xE67906D0U
|
||||
|
||||
#define DBSC_DBPDCNT1(ch) (0xE6790614U + 0x40U * (ch))
|
||||
#define DBSC_DBPDCNT1_0 0xE6790614U
|
||||
#define DBSC_DBPDCNT1_1 0xE6790654U
|
||||
#define DBSC_DBPDCNT1_2 0xE6790694U
|
||||
#define DBSC_DBPDCNT1_3 0xE67906D4U
|
||||
|
||||
#define DBSC_DBPDCNT2(ch) (0xE6790618U + 0x40U * (ch))
|
||||
#define DBSC_DBPDCNT2_0 0xE6790618U
|
||||
#define DBSC_DBPDCNT2_1 0xE6790658U
|
||||
#define DBSC_DBPDCNT2_2 0xE6790698U
|
||||
#define DBSC_DBPDCNT2_3 0xE67906D8U
|
||||
|
||||
#define DBSC_DBPDCNT3(ch) (0xE679061CU + 0x40U * (ch))
|
||||
#define DBSC_DBPDCNT3_0 0xE679061CU
|
||||
#define DBSC_DBPDCNT3_1 0xE679065CU
|
||||
#define DBSC_DBPDCNT3_2 0xE679069CU
|
||||
#define DBSC_DBPDCNT3_3 0xE67906DCU
|
||||
|
||||
#define DBSC_DBPDLK(ch) (0xE6790620U + 0x40U * (ch))
|
||||
#define DBSC_DBPDLK_0 0xE6790620U
|
||||
#define DBSC_DBPDLK_1 0xE6790660U
|
||||
#define DBSC_DBPDLK_2 0xE67906a0U
|
||||
#define DBSC_DBPDLK_3 0xE67906e0U
|
||||
|
||||
#define DBSC_DBPDRGA(ch) (0xE6790624U + 0x40U * (ch))
|
||||
#define DBSC_DBPDRGD(ch) (0xE6790628U + 0x40U * (ch))
|
||||
#define DBSC_DBPDRGA_0 0xE6790624U
|
||||
#define DBSC_DBPDRGD_0 0xE6790628U
|
||||
#define DBSC_DBPDRGA_1 0xE6790664U
|
||||
#define DBSC_DBPDRGD_1 0xE6790668U
|
||||
#define DBSC_DBPDRGA_2 0xE67906A4U
|
||||
#define DBSC_DBPDRGD_2 0xE67906A8U
|
||||
#define DBSC_DBPDRGA_3 0xE67906E4U
|
||||
#define DBSC_DBPDRGD_3 0xE67906E8U
|
||||
|
||||
#define DBSC_DBPDSTAT(ch) (0xE6790630U + 0x40U * (ch))
|
||||
#define DBSC_DBPDSTAT_0 0xE6790630U
|
||||
#define DBSC_DBPDSTAT_1 0xE6790670U
|
||||
#define DBSC_DBPDSTAT_2 0xE67906B0U
|
||||
#define DBSC_DBPDSTAT_3 0xE67906F0U
|
||||
|
||||
#define DBSC_DBBUS0CNF0 0xE6790800U
|
||||
#define DBSC_DBBUS0CNF1 0xE6790804U
|
||||
|
||||
#define DBSC_DBCAM0CNF1 0xE6790904U
|
||||
#define DBSC_DBCAM0CNF2 0xE6790908U
|
||||
#define DBSC_DBCAM0CNF3 0xE679090CU
|
||||
#define DBSC_DBBSWAP 0xE67909F0U
|
||||
#define DBSC_DBBCAMDIS 0xE67909FCU
|
||||
#define DBSC_DBSCHCNT0 0xE6791000U
|
||||
#define DBSC_DBSCHCNT1 0xE6791004U
|
||||
#define DBSC_DBSCHSZ0 0xE6791010U
|
||||
#define DBSC_DBSCHRW0 0xE6791020U
|
||||
#define DBSC_DBSCHRW1 0xE6791024U
|
||||
|
||||
#define DBSC_DBSCHQOS_0(x) (0xE6791030U +0x10U * (x))
|
||||
#define DBSC_DBSCHQOS_1(x) (0xE6791034U +0x10U * (x))
|
||||
#define DBSC_DBSCHQOS_2(x) (0xE6791038U +0x10U * (x))
|
||||
#define DBSC_DBSCHQOS_3(x) (0xE679103CU +0x10U * (x))
|
||||
|
||||
#define DBSC_DBSCTR0 0xE6791700U
|
||||
#define DBSC_DBSCTR1 0xE6791708U
|
||||
#define DBSC_DBSCHRW2 0xE679170CU
|
||||
|
||||
#define DBSC_SCFCTST01(x) (0xE6791700U + 0x08U * (x))
|
||||
#define DBSC_SCFCTST0 0xE6791700U
|
||||
#define DBSC_SCFCTST1 0xE6791708U
|
||||
#define DBSC_SCFCTST2 0xE679170CU
|
||||
|
||||
#define DBSC_DBMRRDR(chab) (0xE6791800U + 0x04U * (chab))
|
||||
#define DBSC_DBMRRDR_0 0xE6791800U
|
||||
#define DBSC_DBMRRDR_1 0xE6791804U
|
||||
#define DBSC_DBMRRDR_2 0xE6791808U
|
||||
#define DBSC_DBMRRDR_3 0xE679180CU
|
||||
#define DBSC_DBMRRDR_4 0xE6791810U
|
||||
#define DBSC_DBMRRDR_5 0xE6791814U
|
||||
#define DBSC_DBMRRDR_6 0xE6791818U
|
||||
#define DBSC_DBMRRDR_7 0xE679181CU
|
||||
|
||||
#define DBSC_DBMEMSWAPCONF0 0xE6792000U
|
||||
#include "../ddr_regs.h"
|
||||
|
||||
#define DBSC_DBMONCONF4 0xE6793010U
|
||||
|
||||
|
@ -264,33 +93,3 @@
|
|||
/* other module */
|
||||
#define THS1_THCTR 0xE6198020U
|
||||
#define THS1_TEMP 0xE6198028U
|
||||
|
||||
#define DBSC_BASE (0xE6790000U)
|
||||
#define DBSC_DBSCHQOS00 (DBSC_BASE + 0x1030U)
|
||||
#define DBSC_DBSCHQOS01 (DBSC_BASE + 0x1034U)
|
||||
#define DBSC_DBSCHQOS02 (DBSC_BASE + 0x1038U)
|
||||
#define DBSC_DBSCHQOS03 (DBSC_BASE + 0x103CU)
|
||||
#define DBSC_DBSCHQOS40 (DBSC_BASE + 0x1070U)
|
||||
#define DBSC_DBSCHQOS41 (DBSC_BASE + 0x1074U)
|
||||
#define DBSC_DBSCHQOS42 (DBSC_BASE + 0x1078U)
|
||||
#define DBSC_DBSCHQOS43 (DBSC_BASE + 0x107CU)
|
||||
#define DBSC_DBSCHQOS90 (DBSC_BASE + 0x10C0U)
|
||||
#define DBSC_DBSCHQOS91 (DBSC_BASE + 0x10C4U)
|
||||
#define DBSC_DBSCHQOS92 (DBSC_BASE + 0x10C8U)
|
||||
#define DBSC_DBSCHQOS93 (DBSC_BASE + 0x10CCU)
|
||||
#define DBSC_DBSCHQOS120 (DBSC_BASE + 0x10F0U)
|
||||
#define DBSC_DBSCHQOS121 (DBSC_BASE + 0x10F4U)
|
||||
#define DBSC_DBSCHQOS122 (DBSC_BASE + 0x10F8U)
|
||||
#define DBSC_DBSCHQOS123 (DBSC_BASE + 0x10FCU)
|
||||
#define DBSC_DBSCHQOS130 (DBSC_BASE + 0x1100U)
|
||||
#define DBSC_DBSCHQOS131 (DBSC_BASE + 0x1104U)
|
||||
#define DBSC_DBSCHQOS132 (DBSC_BASE + 0x1108U)
|
||||
#define DBSC_DBSCHQOS133 (DBSC_BASE + 0x110CU)
|
||||
#define DBSC_DBSCHQOS140 (DBSC_BASE + 0x1110U)
|
||||
#define DBSC_DBSCHQOS141 (DBSC_BASE + 0x1114U)
|
||||
#define DBSC_DBSCHQOS142 (DBSC_BASE + 0x1118U)
|
||||
#define DBSC_DBSCHQOS143 (DBSC_BASE + 0x111CU)
|
||||
#define DBSC_DBSCHQOS150 (DBSC_BASE + 0x1120U)
|
||||
#define DBSC_DBSCHQOS151 (DBSC_BASE + 0x1124U)
|
||||
#define DBSC_DBSCHQOS152 (DBSC_BASE + 0x1128U)
|
||||
#define DBSC_DBSCHQOS153 (DBSC_BASE + 0x112CU)
|
||||
|
|
|
@ -1,5 +1,6 @@
|
|||
/*
|
||||
* Copyright (c) 2018-2019, Renesas Electronics Corporation. All rights reserved.
|
||||
* Copyright (c) 2018-2019, Renesas Electronics Corporation.
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
@ -1178,9 +1179,9 @@
|
|||
#define _reg_PI_TSDO_F1 0x00000493U
|
||||
#define _reg_PI_TSDO_F2 0x00000494U
|
||||
|
||||
#define DDR_REGDEF_ADR(regdef) ((regdef)&0xffff)
|
||||
#define DDR_REGDEF_LEN(regdef) (((regdef)>>16)&0xff)
|
||||
#define DDR_REGDEF_LSB(regdef) (((regdef)>>24)&0xff)
|
||||
#define DDR_REGDEF_ADR(regdef) ((regdef) & 0xffff)
|
||||
#define DDR_REGDEF_LEN(regdef) (((regdef) >> 16) & 0xff)
|
||||
#define DDR_REGDEF_LSB(regdef) (((regdef) >> 24) & 0xff)
|
||||
|
||||
static const uint32_t DDR_REGDEF_TBL[4][1173] = {
|
||||
{
|
||||
|
@ -5882,5 +5883,5 @@ static const uint32_t DDR_REGDEF_TBL[4][1173] = {
|
|||
/*0492*/ 0x0808031dU,
|
||||
/*0493*/ 0x1008031dU,
|
||||
/*0494*/ 0x1808031dU,
|
||||
}
|
||||
}
|
||||
};
|
||||
|
|
|
@ -1,5 +1,6 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
|
||||
* Copyright (c) 2015-2019, Renesas Electronics Corporation.
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
@ -23,418 +24,418 @@
|
|||
#define DDR_PI_REGSET_NUM_H3 181
|
||||
|
||||
static const uint32_t DDR_PHY_SLICE_REGSET_H3[DDR_PHY_SLICE_REGSET_NUM_H3] = {
|
||||
/*0400*/ 0x000004f0,
|
||||
/*0401*/ 0x00000000,
|
||||
/*0402*/ 0x00000000,
|
||||
/*0403*/ 0x00000100,
|
||||
/*0404*/ 0x01003c0c,
|
||||
/*0405*/ 0x02003c0c,
|
||||
/*0406*/ 0x00010300,
|
||||
/*0407*/ 0x04000100,
|
||||
/*0408*/ 0x00000300,
|
||||
/*0409*/ 0x000700c0,
|
||||
/*040a*/ 0x00b00201,
|
||||
/*040b*/ 0x00000020,
|
||||
/*040c*/ 0x00000000,
|
||||
/*040d*/ 0x00000000,
|
||||
/*040e*/ 0x00000000,
|
||||
/*040f*/ 0x00000000,
|
||||
/*0410*/ 0x00000000,
|
||||
/*0411*/ 0x00000000,
|
||||
/*0412*/ 0x00000000,
|
||||
/*0413*/ 0x09000000,
|
||||
/*0414*/ 0x04080000,
|
||||
/*0415*/ 0x04080400,
|
||||
/*0416*/ 0x00000000,
|
||||
/*0417*/ 0x32103210,
|
||||
/*0418*/ 0x00800708,
|
||||
/*0419*/ 0x000f000c,
|
||||
/*041a*/ 0x00000100,
|
||||
/*041b*/ 0x55aa55aa,
|
||||
/*041c*/ 0x33cc33cc,
|
||||
/*041d*/ 0x0ff00ff0,
|
||||
/*041e*/ 0x0f0ff0f0,
|
||||
/*041f*/ 0x00008e38,
|
||||
/*0420*/ 0x76543210,
|
||||
/*0421*/ 0x00000001,
|
||||
/*0422*/ 0x00000000,
|
||||
/*0423*/ 0x00000000,
|
||||
/*0424*/ 0x00000000,
|
||||
/*0425*/ 0x00000000,
|
||||
/*0426*/ 0x00000000,
|
||||
/*0427*/ 0x00000000,
|
||||
/*0428*/ 0x00000000,
|
||||
/*0429*/ 0x00000000,
|
||||
/*042a*/ 0x00000000,
|
||||
/*042b*/ 0x00000000,
|
||||
/*042c*/ 0x00000000,
|
||||
/*042d*/ 0x00000000,
|
||||
/*042e*/ 0x00000000,
|
||||
/*042f*/ 0x00000000,
|
||||
/*0430*/ 0x00000000,
|
||||
/*0431*/ 0x00000000,
|
||||
/*0432*/ 0x00000000,
|
||||
/*0433*/ 0x00200000,
|
||||
/*0434*/ 0x08200820,
|
||||
/*0435*/ 0x08200820,
|
||||
/*0436*/ 0x08200820,
|
||||
/*0437*/ 0x08200820,
|
||||
/*0438*/ 0x08200820,
|
||||
/*0439*/ 0x00000820,
|
||||
/*043a*/ 0x03000300,
|
||||
/*043b*/ 0x03000300,
|
||||
/*043c*/ 0x03000300,
|
||||
/*043d*/ 0x03000300,
|
||||
/*043e*/ 0x00000300,
|
||||
/*043f*/ 0x00000000,
|
||||
/*0440*/ 0x00000000,
|
||||
/*0441*/ 0x00000000,
|
||||
/*0442*/ 0x00000000,
|
||||
/*0443*/ 0x00a000a0,
|
||||
/*0444*/ 0x00a000a0,
|
||||
/*0445*/ 0x00a000a0,
|
||||
/*0446*/ 0x00a000a0,
|
||||
/*0447*/ 0x00a000a0,
|
||||
/*0448*/ 0x00a000a0,
|
||||
/*0449*/ 0x00a000a0,
|
||||
/*044a*/ 0x00a000a0,
|
||||
/*044b*/ 0x00a000a0,
|
||||
/*044c*/ 0x01040109,
|
||||
/*044d*/ 0x00000200,
|
||||
/*044e*/ 0x01000000,
|
||||
/*044f*/ 0x00000200,
|
||||
/*0450*/ 0x4041a141,
|
||||
/*0451*/ 0xc00141a0,
|
||||
/*0452*/ 0x0e0100c0,
|
||||
/*0453*/ 0x0010000c,
|
||||
/*0454*/ 0x0c064208,
|
||||
/*0455*/ 0x000f0c18,
|
||||
/*0456*/ 0x00e00140,
|
||||
/*0457*/ 0x00000c20
|
||||
/*0400*/ 0x000004f0,
|
||||
/*0401*/ 0x00000000,
|
||||
/*0402*/ 0x00000000,
|
||||
/*0403*/ 0x00000100,
|
||||
/*0404*/ 0x01003c0c,
|
||||
/*0405*/ 0x02003c0c,
|
||||
/*0406*/ 0x00010300,
|
||||
/*0407*/ 0x04000100,
|
||||
/*0408*/ 0x00000300,
|
||||
/*0409*/ 0x000700c0,
|
||||
/*040a*/ 0x00b00201,
|
||||
/*040b*/ 0x00000020,
|
||||
/*040c*/ 0x00000000,
|
||||
/*040d*/ 0x00000000,
|
||||
/*040e*/ 0x00000000,
|
||||
/*040f*/ 0x00000000,
|
||||
/*0410*/ 0x00000000,
|
||||
/*0411*/ 0x00000000,
|
||||
/*0412*/ 0x00000000,
|
||||
/*0413*/ 0x09000000,
|
||||
/*0414*/ 0x04080000,
|
||||
/*0415*/ 0x04080400,
|
||||
/*0416*/ 0x00000000,
|
||||
/*0417*/ 0x32103210,
|
||||
/*0418*/ 0x00800708,
|
||||
/*0419*/ 0x000f000c,
|
||||
/*041a*/ 0x00000100,
|
||||
/*041b*/ 0x55aa55aa,
|
||||
/*041c*/ 0x33cc33cc,
|
||||
/*041d*/ 0x0ff00ff0,
|
||||
/*041e*/ 0x0f0ff0f0,
|
||||
/*041f*/ 0x00008e38,
|
||||
/*0420*/ 0x76543210,
|
||||
/*0421*/ 0x00000001,
|
||||
/*0422*/ 0x00000000,
|
||||
/*0423*/ 0x00000000,
|
||||
/*0424*/ 0x00000000,
|
||||
/*0425*/ 0x00000000,
|
||||
/*0426*/ 0x00000000,
|
||||
/*0427*/ 0x00000000,
|
||||
/*0428*/ 0x00000000,
|
||||
/*0429*/ 0x00000000,
|
||||
/*042a*/ 0x00000000,
|
||||
/*042b*/ 0x00000000,
|
||||
/*042c*/ 0x00000000,
|
||||
/*042d*/ 0x00000000,
|
||||
/*042e*/ 0x00000000,
|
||||
/*042f*/ 0x00000000,
|
||||
/*0430*/ 0x00000000,
|
||||
/*0431*/ 0x00000000,
|
||||
/*0432*/ 0x00000000,
|
||||
/*0433*/ 0x00200000,
|
||||
/*0434*/ 0x08200820,
|
||||
/*0435*/ 0x08200820,
|
||||
/*0436*/ 0x08200820,
|
||||
/*0437*/ 0x08200820,
|
||||
/*0438*/ 0x08200820,
|
||||
/*0439*/ 0x00000820,
|
||||
/*043a*/ 0x03000300,
|
||||
/*043b*/ 0x03000300,
|
||||
/*043c*/ 0x03000300,
|
||||
/*043d*/ 0x03000300,
|
||||
/*043e*/ 0x00000300,
|
||||
/*043f*/ 0x00000000,
|
||||
/*0440*/ 0x00000000,
|
||||
/*0441*/ 0x00000000,
|
||||
/*0442*/ 0x00000000,
|
||||
/*0443*/ 0x00a000a0,
|
||||
/*0444*/ 0x00a000a0,
|
||||
/*0445*/ 0x00a000a0,
|
||||
/*0446*/ 0x00a000a0,
|
||||
/*0447*/ 0x00a000a0,
|
||||
/*0448*/ 0x00a000a0,
|
||||
/*0449*/ 0x00a000a0,
|
||||
/*044a*/ 0x00a000a0,
|
||||
/*044b*/ 0x00a000a0,
|
||||
/*044c*/ 0x01040109,
|
||||
/*044d*/ 0x00000200,
|
||||
/*044e*/ 0x01000000,
|
||||
/*044f*/ 0x00000200,
|
||||
/*0450*/ 0x4041a151,
|
||||
/*0451*/ 0xc00141a0,
|
||||
/*0452*/ 0x0e0100c0,
|
||||
/*0453*/ 0x0010000c,
|
||||
/*0454*/ 0x0c064208,
|
||||
/*0455*/ 0x000f0c18,
|
||||
/*0456*/ 0x00e00140,
|
||||
/*0457*/ 0x00000c20
|
||||
};
|
||||
|
||||
static const uint32_t DDR_PHY_ADR_V_REGSET_H3[DDR_PHY_ADR_V_REGSET_NUM_H3] = {
|
||||
/*0600*/ 0x00000000,
|
||||
/*0601*/ 0x00000000,
|
||||
/*0602*/ 0x00000000,
|
||||
/*0603*/ 0x00000000,
|
||||
/*0604*/ 0x00000000,
|
||||
/*0605*/ 0x00000000,
|
||||
/*0606*/ 0x00000002,
|
||||
/*0607*/ 0x00000000,
|
||||
/*0608*/ 0x00000000,
|
||||
/*0609*/ 0x00000000,
|
||||
/*060a*/ 0x00400320,
|
||||
/*060b*/ 0x00000040,
|
||||
/*060c*/ 0x00dcba98,
|
||||
/*060d*/ 0x00000000,
|
||||
/*060e*/ 0x00dcba98,
|
||||
/*060f*/ 0x01000000,
|
||||
/*0610*/ 0x00020003,
|
||||
/*0611*/ 0x00000000,
|
||||
/*0612*/ 0x00000000,
|
||||
/*0613*/ 0x00000000,
|
||||
/*0614*/ 0x00002a01,
|
||||
/*0615*/ 0x00000015,
|
||||
/*0616*/ 0x00000015,
|
||||
/*0617*/ 0x0000002a,
|
||||
/*0618*/ 0x00000033,
|
||||
/*0619*/ 0x0000000c,
|
||||
/*061a*/ 0x0000000c,
|
||||
/*061b*/ 0x00000033,
|
||||
/*061c*/ 0x00418820,
|
||||
/*061d*/ 0x003f0000,
|
||||
/*061e*/ 0x0000003f,
|
||||
/*061f*/ 0x0002006e,
|
||||
/*0620*/ 0x02000200,
|
||||
/*0621*/ 0x02000200,
|
||||
/*0622*/ 0x00000200,
|
||||
/*0623*/ 0x42080010,
|
||||
/*0624*/ 0x00000003
|
||||
/*0600*/ 0x00000000,
|
||||
/*0601*/ 0x00000000,
|
||||
/*0602*/ 0x00000000,
|
||||
/*0603*/ 0x00000000,
|
||||
/*0604*/ 0x00000000,
|
||||
/*0605*/ 0x00000000,
|
||||
/*0606*/ 0x00000002,
|
||||
/*0607*/ 0x00000000,
|
||||
/*0608*/ 0x00000000,
|
||||
/*0609*/ 0x00000000,
|
||||
/*060a*/ 0x00400320,
|
||||
/*060b*/ 0x00000040,
|
||||
/*060c*/ 0x00dcba98,
|
||||
/*060d*/ 0x00000000,
|
||||
/*060e*/ 0x00dcba98,
|
||||
/*060f*/ 0x01000000,
|
||||
/*0610*/ 0x00020003,
|
||||
/*0611*/ 0x00000000,
|
||||
/*0612*/ 0x00000000,
|
||||
/*0613*/ 0x00000000,
|
||||
/*0614*/ 0x00002a01,
|
||||
/*0615*/ 0x00000015,
|
||||
/*0616*/ 0x00000015,
|
||||
/*0617*/ 0x0000002a,
|
||||
/*0618*/ 0x00000033,
|
||||
/*0619*/ 0x0000000c,
|
||||
/*061a*/ 0x0000000c,
|
||||
/*061b*/ 0x00000033,
|
||||
/*061c*/ 0x00418820,
|
||||
/*061d*/ 0x003f0000,
|
||||
/*061e*/ 0x0000003f,
|
||||
/*061f*/ 0x0002006e,
|
||||
/*0620*/ 0x02000200,
|
||||
/*0621*/ 0x02000200,
|
||||
/*0622*/ 0x00000200,
|
||||
/*0623*/ 0x42080010,
|
||||
/*0624*/ 0x00000003
|
||||
};
|
||||
|
||||
static const uint32_t DDR_PHY_ADR_I_REGSET_H3[DDR_PHY_ADR_I_REGSET_NUM_H3] = {
|
||||
/*0680*/ 0x04040404,
|
||||
/*0681*/ 0x00000404,
|
||||
/*0682*/ 0x00000000,
|
||||
/*0683*/ 0x00000000,
|
||||
/*0684*/ 0x00000000,
|
||||
/*0685*/ 0x00000000,
|
||||
/*0686*/ 0x00000002,
|
||||
/*0687*/ 0x00000000,
|
||||
/*0688*/ 0x00000000,
|
||||
/*0689*/ 0x00000000,
|
||||
/*068a*/ 0x00400320,
|
||||
/*068b*/ 0x00000040,
|
||||
/*068c*/ 0x00000000,
|
||||
/*068d*/ 0x00000000,
|
||||
/*068e*/ 0x00000000,
|
||||
/*068f*/ 0x01000000,
|
||||
/*0690*/ 0x00020003,
|
||||
/*0691*/ 0x00000000,
|
||||
/*0692*/ 0x00000000,
|
||||
/*0693*/ 0x00000000,
|
||||
/*0694*/ 0x00002a01,
|
||||
/*0695*/ 0x00000015,
|
||||
/*0696*/ 0x00000015,
|
||||
/*0697*/ 0x0000002a,
|
||||
/*0698*/ 0x00000033,
|
||||
/*0699*/ 0x0000000c,
|
||||
/*069a*/ 0x0000000c,
|
||||
/*069b*/ 0x00000033,
|
||||
/*069c*/ 0x00000000,
|
||||
/*069d*/ 0x00000000,
|
||||
/*069e*/ 0x00000000,
|
||||
/*069f*/ 0x0002006e,
|
||||
/*06a0*/ 0x02000200,
|
||||
/*06a1*/ 0x02000200,
|
||||
/*06a2*/ 0x00000200,
|
||||
/*06a3*/ 0x42080010,
|
||||
/*06a4*/ 0x00000003
|
||||
/*0680*/ 0x04040404,
|
||||
/*0681*/ 0x00000404,
|
||||
/*0682*/ 0x00000000,
|
||||
/*0683*/ 0x00000000,
|
||||
/*0684*/ 0x00000000,
|
||||
/*0685*/ 0x00000000,
|
||||
/*0686*/ 0x00000002,
|
||||
/*0687*/ 0x00000000,
|
||||
/*0688*/ 0x00000000,
|
||||
/*0689*/ 0x00000000,
|
||||
/*068a*/ 0x00400320,
|
||||
/*068b*/ 0x00000040,
|
||||
/*068c*/ 0x00000000,
|
||||
/*068d*/ 0x00000000,
|
||||
/*068e*/ 0x00000000,
|
||||
/*068f*/ 0x01000000,
|
||||
/*0690*/ 0x00020003,
|
||||
/*0691*/ 0x00000000,
|
||||
/*0692*/ 0x00000000,
|
||||
/*0693*/ 0x00000000,
|
||||
/*0694*/ 0x00002a01,
|
||||
/*0695*/ 0x00000015,
|
||||
/*0696*/ 0x00000015,
|
||||
/*0697*/ 0x0000002a,
|
||||
/*0698*/ 0x00000033,
|
||||
/*0699*/ 0x0000000c,
|
||||
/*069a*/ 0x0000000c,
|
||||
/*069b*/ 0x00000033,
|
||||
/*069c*/ 0x00000000,
|
||||
/*069d*/ 0x00000000,
|
||||
/*069e*/ 0x00000000,
|
||||
/*069f*/ 0x0002006e,
|
||||
/*06a0*/ 0x02000200,
|
||||
/*06a1*/ 0x02000200,
|
||||
/*06a2*/ 0x00000200,
|
||||
/*06a3*/ 0x42080010,
|
||||
/*06a4*/ 0x00000003
|
||||
};
|
||||
|
||||
static const uint32_t DDR_PHY_ADR_G_REGSET_H3[DDR_PHY_ADR_G_REGSET_NUM_H3] = {
|
||||
/*0700*/ 0x00000001,
|
||||
/*0701*/ 0x00000000,
|
||||
/*0702*/ 0x00000005,
|
||||
/*0703*/ 0x04000f00,
|
||||
/*0704*/ 0x00020080,
|
||||
/*0705*/ 0x00020055,
|
||||
/*0706*/ 0x00000000,
|
||||
/*0707*/ 0x00000000,
|
||||
/*0708*/ 0x00000000,
|
||||
/*0709*/ 0x00000050,
|
||||
/*070a*/ 0x00000000,
|
||||
/*070b*/ 0x01010100,
|
||||
/*070c*/ 0x00000200,
|
||||
/*070d*/ 0x00001102,
|
||||
/*070e*/ 0x00000000,
|
||||
/*070f*/ 0x000f1f00,
|
||||
/*0710*/ 0x0f1f0f1f,
|
||||
/*0711*/ 0x0f1f0f1f,
|
||||
/*0712*/ 0x00020003,
|
||||
/*0713*/ 0x02000200,
|
||||
/*0714*/ 0x00000200,
|
||||
/*0715*/ 0x00001102,
|
||||
/*0716*/ 0x00000064,
|
||||
/*0717*/ 0x00000000,
|
||||
/*0718*/ 0x00000000,
|
||||
/*0719*/ 0x00000502,
|
||||
/*071a*/ 0x027f6e00,
|
||||
/*071b*/ 0x007f007f,
|
||||
/*071c*/ 0x00007f3c,
|
||||
/*071d*/ 0x00047f6e,
|
||||
/*071e*/ 0x0003154f,
|
||||
/*071f*/ 0x0001154f,
|
||||
/*0720*/ 0x0001154f,
|
||||
/*0721*/ 0x0001154f,
|
||||
/*0722*/ 0x0001154f,
|
||||
/*0723*/ 0x00003fee,
|
||||
/*0724*/ 0x0001154f,
|
||||
/*0725*/ 0x00003fee,
|
||||
/*0726*/ 0x0001154f,
|
||||
/*0727*/ 0x00007f3c,
|
||||
/*0728*/ 0x0001154f,
|
||||
/*0729*/ 0x00000000,
|
||||
/*072a*/ 0x00000000,
|
||||
/*072b*/ 0x00000000,
|
||||
/*072c*/ 0x65000000,
|
||||
/*072d*/ 0x00000000,
|
||||
/*072e*/ 0x00000000,
|
||||
/*072f*/ 0x00000201,
|
||||
/*0730*/ 0x00000000,
|
||||
/*0731*/ 0x00000000,
|
||||
/*0732*/ 0x00000000,
|
||||
/*0733*/ 0x00000000,
|
||||
/*0734*/ 0x00000000,
|
||||
/*0735*/ 0x00000000,
|
||||
/*0736*/ 0x00000000,
|
||||
/*0737*/ 0x00000000,
|
||||
/*0738*/ 0x00000000,
|
||||
/*0739*/ 0x00000000,
|
||||
/*073a*/ 0x00000000
|
||||
/*0700*/ 0x00000001,
|
||||
/*0701*/ 0x00000000,
|
||||
/*0702*/ 0x00000005,
|
||||
/*0703*/ 0x04000f00,
|
||||
/*0704*/ 0x00020080,
|
||||
/*0705*/ 0x00020055,
|
||||
/*0706*/ 0x00000000,
|
||||
/*0707*/ 0x00000000,
|
||||
/*0708*/ 0x00000000,
|
||||
/*0709*/ 0x00000050,
|
||||
/*070a*/ 0x00000000,
|
||||
/*070b*/ 0x01010100,
|
||||
/*070c*/ 0x00000200,
|
||||
/*070d*/ 0x00001102,
|
||||
/*070e*/ 0x00000000,
|
||||
/*070f*/ 0x000f1f00,
|
||||
/*0710*/ 0x0f1f0f1f,
|
||||
/*0711*/ 0x0f1f0f1f,
|
||||
/*0712*/ 0x00020003,
|
||||
/*0713*/ 0x02000200,
|
||||
/*0714*/ 0x00000200,
|
||||
/*0715*/ 0x00001102,
|
||||
/*0716*/ 0x00000064,
|
||||
/*0717*/ 0x00000000,
|
||||
/*0718*/ 0x00000000,
|
||||
/*0719*/ 0x00000502,
|
||||
/*071a*/ 0x027f6e00,
|
||||
/*071b*/ 0x007f007f,
|
||||
/*071c*/ 0x00007f3c,
|
||||
/*071d*/ 0x00047f6e,
|
||||
/*071e*/ 0x0003154f,
|
||||
/*071f*/ 0x0001154f,
|
||||
/*0720*/ 0x0001154f,
|
||||
/*0721*/ 0x0001154f,
|
||||
/*0722*/ 0x0001154f,
|
||||
/*0723*/ 0x00003fee,
|
||||
/*0724*/ 0x0001154f,
|
||||
/*0725*/ 0x00003fee,
|
||||
/*0726*/ 0x0001154f,
|
||||
/*0727*/ 0x00007f3c,
|
||||
/*0728*/ 0x0001154f,
|
||||
/*0729*/ 0x00000000,
|
||||
/*072a*/ 0x00000000,
|
||||
/*072b*/ 0x00000000,
|
||||
/*072c*/ 0x65000000,
|
||||
/*072d*/ 0x00000000,
|
||||
/*072e*/ 0x00000000,
|
||||
/*072f*/ 0x00000201,
|
||||
/*0730*/ 0x00000000,
|
||||
/*0731*/ 0x00000000,
|
||||
/*0732*/ 0x00000000,
|
||||
/*0733*/ 0x00000000,
|
||||
/*0734*/ 0x00000000,
|
||||
/*0735*/ 0x00000000,
|
||||
/*0736*/ 0x00000000,
|
||||
/*0737*/ 0x00000000,
|
||||
/*0738*/ 0x00000000,
|
||||
/*0739*/ 0x00000000,
|
||||
/*073a*/ 0x00000000
|
||||
};
|
||||
|
||||
static const uint32_t DDR_PI_REGSET_H3[DDR_PI_REGSET_NUM_H3] = {
|
||||
/*0200*/ 0x00000b00,
|
||||
/*0201*/ 0x00000100,
|
||||
/*0202*/ 0x00000000,
|
||||
/*0203*/ 0x0000ffff,
|
||||
/*0204*/ 0x00000000,
|
||||
/*0205*/ 0x0000ffff,
|
||||
/*0206*/ 0x00000000,
|
||||
/*0207*/ 0x304cffff,
|
||||
/*0208*/ 0x00000200,
|
||||
/*0209*/ 0x00000200,
|
||||
/*020a*/ 0x00000200,
|
||||
/*020b*/ 0x00000200,
|
||||
/*020c*/ 0x0000304c,
|
||||
/*020d*/ 0x00000200,
|
||||
/*020e*/ 0x00000200,
|
||||
/*020f*/ 0x00000200,
|
||||
/*0210*/ 0x00000200,
|
||||
/*0211*/ 0x0000304c,
|
||||
/*0212*/ 0x00000200,
|
||||
/*0213*/ 0x00000200,
|
||||
/*0214*/ 0x00000200,
|
||||
/*0215*/ 0x00000200,
|
||||
/*0216*/ 0x00010000,
|
||||
/*0217*/ 0x00000003,
|
||||
/*0218*/ 0x01000001,
|
||||
/*0219*/ 0x00000000,
|
||||
/*021a*/ 0x00000000,
|
||||
/*021b*/ 0x00000000,
|
||||
/*021c*/ 0x00000000,
|
||||
/*021d*/ 0x00000000,
|
||||
/*021e*/ 0x00000000,
|
||||
/*021f*/ 0x00000000,
|
||||
/*0220*/ 0x00000000,
|
||||
/*0221*/ 0x00000000,
|
||||
/*0222*/ 0x00000000,
|
||||
/*0223*/ 0x00000000,
|
||||
/*0224*/ 0x00000000,
|
||||
/*0225*/ 0x00000000,
|
||||
/*0226*/ 0x00000000,
|
||||
/*0227*/ 0x00000000,
|
||||
/*0228*/ 0x00000000,
|
||||
/*0229*/ 0x0f000101,
|
||||
/*022a*/ 0x08492d25,
|
||||
/*022b*/ 0x500e0c04,
|
||||
/*022c*/ 0x0002500e,
|
||||
/*022d*/ 0x00460003,
|
||||
/*022e*/ 0x182600cf,
|
||||
/*022f*/ 0x182600cf,
|
||||
/*0230*/ 0x00000005,
|
||||
/*0231*/ 0x00000000,
|
||||
/*0232*/ 0x00000000,
|
||||
/*0233*/ 0x00000000,
|
||||
/*0234*/ 0x00000000,
|
||||
/*0235*/ 0x00000000,
|
||||
/*0236*/ 0x00000000,
|
||||
/*0237*/ 0x00000000,
|
||||
/*0238*/ 0x01000000,
|
||||
/*0239*/ 0x00040404,
|
||||
/*023a*/ 0x01280a00,
|
||||
/*023b*/ 0x00000000,
|
||||
/*023c*/ 0x000f0000,
|
||||
/*023d*/ 0x00001803,
|
||||
/*023e*/ 0x00000000,
|
||||
/*023f*/ 0x00000000,
|
||||
/*0240*/ 0x00060002,
|
||||
/*0241*/ 0x00010001,
|
||||
/*0242*/ 0x01000101,
|
||||
/*0243*/ 0x04020201,
|
||||
/*0244*/ 0x00080804,
|
||||
/*0245*/ 0x00000000,
|
||||
/*0246*/ 0x08030000,
|
||||
/*0247*/ 0x15150408,
|
||||
/*0248*/ 0x00000000,
|
||||
/*0249*/ 0x00000000,
|
||||
/*024a*/ 0x00000000,
|
||||
/*024b*/ 0x001e0f0f,
|
||||
/*024c*/ 0x00000000,
|
||||
/*024d*/ 0x01000300,
|
||||
/*024e*/ 0x00000000,
|
||||
/*024f*/ 0x00000000,
|
||||
/*0250*/ 0x01000000,
|
||||
/*0251*/ 0x00010101,
|
||||
/*0252*/ 0x000e0e0e,
|
||||
/*0253*/ 0x000c0c0c,
|
||||
/*0254*/ 0x02060601,
|
||||
/*0255*/ 0x00000000,
|
||||
/*0256*/ 0x00000003,
|
||||
/*0257*/ 0x00181703,
|
||||
/*0258*/ 0x00280006,
|
||||
/*0259*/ 0x00280016,
|
||||
/*025a*/ 0x00000016,
|
||||
/*025b*/ 0x00000000,
|
||||
/*025c*/ 0x00000000,
|
||||
/*025d*/ 0x00000000,
|
||||
/*025e*/ 0x140a0000,
|
||||
/*025f*/ 0x0005010a,
|
||||
/*0260*/ 0x03018d03,
|
||||
/*0261*/ 0x000a018d,
|
||||
/*0262*/ 0x00060100,
|
||||
/*0263*/ 0x01000006,
|
||||
/*0264*/ 0x018e018e,
|
||||
/*0265*/ 0x018e0100,
|
||||
/*0266*/ 0x1111018e,
|
||||
/*0267*/ 0x10010204,
|
||||
/*0268*/ 0x09090650,
|
||||
/*0269*/ 0x20110202,
|
||||
/*026a*/ 0x00201000,
|
||||
/*026b*/ 0x00201000,
|
||||
/*026c*/ 0x04041000,
|
||||
/*026d*/ 0x18020100,
|
||||
/*026e*/ 0x00010118,
|
||||
/*026f*/ 0x004b004a,
|
||||
/*0270*/ 0x050f0000,
|
||||
/*0271*/ 0x0c01021e,
|
||||
/*0272*/ 0x34000000,
|
||||
/*0273*/ 0x00000000,
|
||||
/*0274*/ 0x00000000,
|
||||
/*0275*/ 0x00000000,
|
||||
/*0276*/ 0x312ed400,
|
||||
/*0277*/ 0xd4111132,
|
||||
/*0278*/ 0x1132312e,
|
||||
/*0279*/ 0x312ed411,
|
||||
/*027a*/ 0x00111132,
|
||||
/*027b*/ 0x32312ed4,
|
||||
/*027c*/ 0x2ed41111,
|
||||
/*027d*/ 0x11113231,
|
||||
/*027e*/ 0x32312ed4,
|
||||
/*027f*/ 0xd4001111,
|
||||
/*0280*/ 0x1132312e,
|
||||
/*0281*/ 0x312ed411,
|
||||
/*0282*/ 0xd4111132,
|
||||
/*0283*/ 0x1132312e,
|
||||
/*0284*/ 0x2ed40011,
|
||||
/*0285*/ 0x11113231,
|
||||
/*0286*/ 0x32312ed4,
|
||||
/*0287*/ 0x2ed41111,
|
||||
/*0288*/ 0x11113231,
|
||||
/*0289*/ 0x00020000,
|
||||
/*028a*/ 0x018d018d,
|
||||
/*028b*/ 0x0c08018d,
|
||||
/*028c*/ 0x1f121d22,
|
||||
/*028d*/ 0x4301b344,
|
||||
/*028e*/ 0x10172006,
|
||||
/*028f*/ 0x121d220c,
|
||||
/*0290*/ 0x01b3441f,
|
||||
/*0291*/ 0x17200643,
|
||||
/*0292*/ 0x1d220c10,
|
||||
/*0293*/ 0x00001f12,
|
||||
/*0294*/ 0x4301b344,
|
||||
/*0295*/ 0x10172006,
|
||||
/*0296*/ 0x00020002,
|
||||
/*0297*/ 0x00020002,
|
||||
/*0298*/ 0x00020002,
|
||||
/*0299*/ 0x00020002,
|
||||
/*029a*/ 0x00020002,
|
||||
/*029b*/ 0x00000000,
|
||||
/*029c*/ 0x00000000,
|
||||
/*029d*/ 0x00000000,
|
||||
/*029e*/ 0x00000000,
|
||||
/*029f*/ 0x00000000,
|
||||
/*02a0*/ 0x00000000,
|
||||
/*02a1*/ 0x00000000,
|
||||
/*02a2*/ 0x00000000,
|
||||
/*02a3*/ 0x00000000,
|
||||
/*02a4*/ 0x00000000,
|
||||
/*02a5*/ 0x00000000,
|
||||
/*02a6*/ 0x00000000,
|
||||
/*02a7*/ 0x01000400,
|
||||
/*02a8*/ 0x00304c00,
|
||||
/*02a9*/ 0x0001e2f8,
|
||||
/*02aa*/ 0x0000304c,
|
||||
/*02ab*/ 0x0001e2f8,
|
||||
/*02ac*/ 0x0000304c,
|
||||
/*02ad*/ 0x0001e2f8,
|
||||
/*02ae*/ 0x08000000,
|
||||
/*02af*/ 0x00000100,
|
||||
/*02b0*/ 0x00000000,
|
||||
/*02b1*/ 0x00000000,
|
||||
/*02b2*/ 0x00000000,
|
||||
/*02b3*/ 0x00000000,
|
||||
/*02b4*/ 0x00000002
|
||||
/*0200*/ 0x00000b00,
|
||||
/*0201*/ 0x00000100,
|
||||
/*0202*/ 0x00000000,
|
||||
/*0203*/ 0x0000ffff,
|
||||
/*0204*/ 0x00000000,
|
||||
/*0205*/ 0x0000ffff,
|
||||
/*0206*/ 0x00000000,
|
||||
/*0207*/ 0x304cffff,
|
||||
/*0208*/ 0x00000200,
|
||||
/*0209*/ 0x00000200,
|
||||
/*020a*/ 0x00000200,
|
||||
/*020b*/ 0x00000200,
|
||||
/*020c*/ 0x0000304c,
|
||||
/*020d*/ 0x00000200,
|
||||
/*020e*/ 0x00000200,
|
||||
/*020f*/ 0x00000200,
|
||||
/*0210*/ 0x00000200,
|
||||
/*0211*/ 0x0000304c,
|
||||
/*0212*/ 0x00000200,
|
||||
/*0213*/ 0x00000200,
|
||||
/*0214*/ 0x00000200,
|
||||
/*0215*/ 0x00000200,
|
||||
/*0216*/ 0x00010000,
|
||||
/*0217*/ 0x00000003,
|
||||
/*0218*/ 0x01000001,
|
||||
/*0219*/ 0x00000000,
|
||||
/*021a*/ 0x00000000,
|
||||
/*021b*/ 0x00000000,
|
||||
/*021c*/ 0x00000000,
|
||||
/*021d*/ 0x00000000,
|
||||
/*021e*/ 0x00000000,
|
||||
/*021f*/ 0x00000000,
|
||||
/*0220*/ 0x00000000,
|
||||
/*0221*/ 0x00000000,
|
||||
/*0222*/ 0x00000000,
|
||||
/*0223*/ 0x00000000,
|
||||
/*0224*/ 0x00000000,
|
||||
/*0225*/ 0x00000000,
|
||||
/*0226*/ 0x00000000,
|
||||
/*0227*/ 0x00000000,
|
||||
/*0228*/ 0x00000000,
|
||||
/*0229*/ 0x0f000101,
|
||||
/*022a*/ 0x08492d25,
|
||||
/*022b*/ 0x500e0c04,
|
||||
/*022c*/ 0x0002500e,
|
||||
/*022d*/ 0x00460003,
|
||||
/*022e*/ 0x182600cf,
|
||||
/*022f*/ 0x182600cf,
|
||||
/*0230*/ 0x00000005,
|
||||
/*0231*/ 0x00000000,
|
||||
/*0232*/ 0x00000000,
|
||||
/*0233*/ 0x00000000,
|
||||
/*0234*/ 0x00000000,
|
||||
/*0235*/ 0x00000000,
|
||||
/*0236*/ 0x00000000,
|
||||
/*0237*/ 0x00000000,
|
||||
/*0238*/ 0x01000000,
|
||||
/*0239*/ 0x00040404,
|
||||
/*023a*/ 0x01280a00,
|
||||
/*023b*/ 0x00000000,
|
||||
/*023c*/ 0x000f0000,
|
||||
/*023d*/ 0x00001803,
|
||||
/*023e*/ 0x00000000,
|
||||
/*023f*/ 0x00000000,
|
||||
/*0240*/ 0x00060002,
|
||||
/*0241*/ 0x00010001,
|
||||
/*0242*/ 0x01000101,
|
||||
/*0243*/ 0x04020201,
|
||||
/*0244*/ 0x00080804,
|
||||
/*0245*/ 0x00000000,
|
||||
/*0246*/ 0x08030000,
|
||||
/*0247*/ 0x15150408,
|
||||
/*0248*/ 0x00000000,
|
||||
/*0249*/ 0x00000000,
|
||||
/*024a*/ 0x00000000,
|
||||
/*024b*/ 0x001e0f0f,
|
||||
/*024c*/ 0x00000000,
|
||||
/*024d*/ 0x01000300,
|
||||
/*024e*/ 0x00000000,
|
||||
/*024f*/ 0x00000000,
|
||||
/*0250*/ 0x01000000,
|
||||
/*0251*/ 0x00010101,
|
||||
/*0252*/ 0x000e0e0e,
|
||||
/*0253*/ 0x000c0c0c,
|
||||
/*0254*/ 0x02060601,
|
||||
/*0255*/ 0x00000000,
|
||||
/*0256*/ 0x00000003,
|
||||
/*0257*/ 0x00181703,
|
||||
/*0258*/ 0x00280006,
|
||||
/*0259*/ 0x00280016,
|
||||
/*025a*/ 0x00000016,
|
||||
/*025b*/ 0x00000000,
|
||||
/*025c*/ 0x00000000,
|
||||
/*025d*/ 0x00000000,
|
||||
/*025e*/ 0x140a0000,
|
||||
/*025f*/ 0x0005010a,
|
||||
/*0260*/ 0x03018d03,
|
||||
/*0261*/ 0x000a018d,
|
||||
/*0262*/ 0x00060100,
|
||||
/*0263*/ 0x01000006,
|
||||
/*0264*/ 0x018e018e,
|
||||
/*0265*/ 0x018e0100,
|
||||
/*0266*/ 0x1111018e,
|
||||
/*0267*/ 0x10010204,
|
||||
/*0268*/ 0x09090650,
|
||||
/*0269*/ 0x20110202,
|
||||
/*026a*/ 0x00201000,
|
||||
/*026b*/ 0x00201000,
|
||||
/*026c*/ 0x04041000,
|
||||
/*026d*/ 0x18020100,
|
||||
/*026e*/ 0x00010118,
|
||||
/*026f*/ 0x004b004a,
|
||||
/*0270*/ 0x050f0000,
|
||||
/*0271*/ 0x0c01021e,
|
||||
/*0272*/ 0x34000000,
|
||||
/*0273*/ 0x00000000,
|
||||
/*0274*/ 0x00000000,
|
||||
/*0275*/ 0x00000000,
|
||||
/*0276*/ 0x312ed400,
|
||||
/*0277*/ 0xd4111132,
|
||||
/*0278*/ 0x1132312e,
|
||||
/*0279*/ 0x312ed411,
|
||||
/*027a*/ 0x00111132,
|
||||
/*027b*/ 0x32312ed4,
|
||||
/*027c*/ 0x2ed41111,
|
||||
/*027d*/ 0x11113231,
|
||||
/*027e*/ 0x32312ed4,
|
||||
/*027f*/ 0xd4001111,
|
||||
/*0280*/ 0x1132312e,
|
||||
/*0281*/ 0x312ed411,
|
||||
/*0282*/ 0xd4111132,
|
||||
/*0283*/ 0x1132312e,
|
||||
/*0284*/ 0x2ed40011,
|
||||
/*0285*/ 0x11113231,
|
||||
/*0286*/ 0x32312ed4,
|
||||
/*0287*/ 0x2ed41111,
|
||||
/*0288*/ 0x11113231,
|
||||
/*0289*/ 0x00020000,
|
||||
/*028a*/ 0x018d018d,
|
||||
/*028b*/ 0x0c08018d,
|
||||
/*028c*/ 0x1f121d22,
|
||||
/*028d*/ 0x4301b344,
|
||||
/*028e*/ 0x10172006,
|
||||
/*028f*/ 0x121d220c,
|
||||
/*0290*/ 0x01b3441f,
|
||||
/*0291*/ 0x17200643,
|
||||
/*0292*/ 0x1d220c10,
|
||||
/*0293*/ 0x00001f12,
|
||||
/*0294*/ 0x4301b344,
|
||||
/*0295*/ 0x10172006,
|
||||
/*0296*/ 0x00020002,
|
||||
/*0297*/ 0x00020002,
|
||||
/*0298*/ 0x00020002,
|
||||
/*0299*/ 0x00020002,
|
||||
/*029a*/ 0x00020002,
|
||||
/*029b*/ 0x00000000,
|
||||
/*029c*/ 0x00000000,
|
||||
/*029d*/ 0x00000000,
|
||||
/*029e*/ 0x00000000,
|
||||
/*029f*/ 0x00000000,
|
||||
/*02a0*/ 0x00000000,
|
||||
/*02a1*/ 0x00000000,
|
||||
/*02a2*/ 0x00000000,
|
||||
/*02a3*/ 0x00000000,
|
||||
/*02a4*/ 0x00000000,
|
||||
/*02a5*/ 0x00000000,
|
||||
/*02a6*/ 0x00000000,
|
||||
/*02a7*/ 0x01000400,
|
||||
/*02a8*/ 0x00304c00,
|
||||
/*02a9*/ 0x0001e2f8,
|
||||
/*02aa*/ 0x0000304c,
|
||||
/*02ab*/ 0x0001e2f8,
|
||||
/*02ac*/ 0x0000304c,
|
||||
/*02ad*/ 0x0001e2f8,
|
||||
/*02ae*/ 0x08000000,
|
||||
/*02af*/ 0x00000100,
|
||||
/*02b0*/ 0x00000000,
|
||||
/*02b1*/ 0x00000000,
|
||||
/*02b2*/ 0x00000000,
|
||||
/*02b3*/ 0x00000000,
|
||||
/*02b4*/ 0x00000002
|
||||
};
|
||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -1,5 +1,6 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
|
||||
* Copyright (c) 2015-2019, Renesas Electronics Corporation.
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
@ -23,445 +24,445 @@
|
|||
#define DDR_PI_REGSET_NUM_M3 202
|
||||
|
||||
static const uint32_t DDR_PHY_SLICE_REGSET_M3[DDR_PHY_SLICE_REGSET_NUM_M3] = {
|
||||
/*0800*/ 0x76543210,
|
||||
/*0801*/ 0x0004f008,
|
||||
/*0802*/ 0x00000000,
|
||||
/*0803*/ 0x00000000,
|
||||
/*0804*/ 0x00010000,
|
||||
/*0805*/ 0x036e6e0e,
|
||||
/*0806*/ 0x026e6e0e,
|
||||
/*0807*/ 0x00010300,
|
||||
/*0808*/ 0x04000100,
|
||||
/*0809*/ 0x00000300,
|
||||
/*080a*/ 0x001700c0,
|
||||
/*080b*/ 0x00b00201,
|
||||
/*080c*/ 0x00030020,
|
||||
/*080d*/ 0x00000000,
|
||||
/*080e*/ 0x00000000,
|
||||
/*080f*/ 0x00000000,
|
||||
/*0810*/ 0x00000000,
|
||||
/*0811*/ 0x00000000,
|
||||
/*0812*/ 0x00000000,
|
||||
/*0813*/ 0x00000000,
|
||||
/*0814*/ 0x09000000,
|
||||
/*0815*/ 0x04080000,
|
||||
/*0816*/ 0x04080400,
|
||||
/*0817*/ 0x00000000,
|
||||
/*0818*/ 0x32103210,
|
||||
/*0819*/ 0x00800708,
|
||||
/*081a*/ 0x000f000c,
|
||||
/*081b*/ 0x00000100,
|
||||
/*081c*/ 0x55aa55aa,
|
||||
/*081d*/ 0x33cc33cc,
|
||||
/*081e*/ 0x0ff00ff0,
|
||||
/*081f*/ 0x0f0ff0f0,
|
||||
/*0820*/ 0x00018e38,
|
||||
/*0821*/ 0x00000000,
|
||||
/*0822*/ 0x00000000,
|
||||
/*0823*/ 0x00000000,
|
||||
/*0824*/ 0x00000000,
|
||||
/*0825*/ 0x00000000,
|
||||
/*0826*/ 0x00000000,
|
||||
/*0827*/ 0x00000000,
|
||||
/*0828*/ 0x00000000,
|
||||
/*0829*/ 0x00000000,
|
||||
/*082a*/ 0x00000000,
|
||||
/*082b*/ 0x00000000,
|
||||
/*082c*/ 0x00000000,
|
||||
/*082d*/ 0x00000000,
|
||||
/*082e*/ 0x00000000,
|
||||
/*082f*/ 0x00000000,
|
||||
/*0830*/ 0x00000000,
|
||||
/*0831*/ 0x00000000,
|
||||
/*0832*/ 0x00000000,
|
||||
/*0833*/ 0x00200000,
|
||||
/*0834*/ 0x08200820,
|
||||
/*0835*/ 0x08200820,
|
||||
/*0836*/ 0x08200820,
|
||||
/*0837*/ 0x08200820,
|
||||
/*0838*/ 0x08200820,
|
||||
/*0839*/ 0x00000820,
|
||||
/*083a*/ 0x03000300,
|
||||
/*083b*/ 0x03000300,
|
||||
/*083c*/ 0x03000300,
|
||||
/*083d*/ 0x03000300,
|
||||
/*083e*/ 0x00000300,
|
||||
/*083f*/ 0x00000000,
|
||||
/*0840*/ 0x00000000,
|
||||
/*0841*/ 0x00000000,
|
||||
/*0842*/ 0x00000000,
|
||||
/*0843*/ 0x00a00000,
|
||||
/*0844*/ 0x00a000a0,
|
||||
/*0845*/ 0x00a000a0,
|
||||
/*0846*/ 0x00a000a0,
|
||||
/*0847*/ 0x00a000a0,
|
||||
/*0848*/ 0x00a000a0,
|
||||
/*0849*/ 0x00a000a0,
|
||||
/*084a*/ 0x00a000a0,
|
||||
/*084b*/ 0x00a000a0,
|
||||
/*084c*/ 0x010900a0,
|
||||
/*084d*/ 0x02000104,
|
||||
/*084e*/ 0x00000000,
|
||||
/*084f*/ 0x00010000,
|
||||
/*0850*/ 0x00000200,
|
||||
/*0851*/ 0x4041a141,
|
||||
/*0852*/ 0xc00141a0,
|
||||
/*0853*/ 0x0e0100c0,
|
||||
/*0854*/ 0x0010000c,
|
||||
/*0855*/ 0x0c064208,
|
||||
/*0856*/ 0x000f0c18,
|
||||
/*0857*/ 0x00e00140,
|
||||
/*0858*/ 0x00000c20
|
||||
/*0800*/ 0x76543210,
|
||||
/*0801*/ 0x0004f008,
|
||||
/*0802*/ 0x00000000,
|
||||
/*0803*/ 0x00000000,
|
||||
/*0804*/ 0x00010000,
|
||||
/*0805*/ 0x036e6e0e,
|
||||
/*0806*/ 0x026e6e0e,
|
||||
/*0807*/ 0x00010300,
|
||||
/*0808*/ 0x04000100,
|
||||
/*0809*/ 0x00000300,
|
||||
/*080a*/ 0x001700c0,
|
||||
/*080b*/ 0x00b00201,
|
||||
/*080c*/ 0x00030020,
|
||||
/*080d*/ 0x00000000,
|
||||
/*080e*/ 0x00000000,
|
||||
/*080f*/ 0x00000000,
|
||||
/*0810*/ 0x00000000,
|
||||
/*0811*/ 0x00000000,
|
||||
/*0812*/ 0x00000000,
|
||||
/*0813*/ 0x00000000,
|
||||
/*0814*/ 0x09000000,
|
||||
/*0815*/ 0x04080000,
|
||||
/*0816*/ 0x04080400,
|
||||
/*0817*/ 0x00000000,
|
||||
/*0818*/ 0x32103210,
|
||||
/*0819*/ 0x00800708,
|
||||
/*081a*/ 0x000f000c,
|
||||
/*081b*/ 0x00000100,
|
||||
/*081c*/ 0x55aa55aa,
|
||||
/*081d*/ 0x33cc33cc,
|
||||
/*081e*/ 0x0ff00ff0,
|
||||
/*081f*/ 0x0f0ff0f0,
|
||||
/*0820*/ 0x00018e38,
|
||||
/*0821*/ 0x00000000,
|
||||
/*0822*/ 0x00000000,
|
||||
/*0823*/ 0x00000000,
|
||||
/*0824*/ 0x00000000,
|
||||
/*0825*/ 0x00000000,
|
||||
/*0826*/ 0x00000000,
|
||||
/*0827*/ 0x00000000,
|
||||
/*0828*/ 0x00000000,
|
||||
/*0829*/ 0x00000000,
|
||||
/*082a*/ 0x00000000,
|
||||
/*082b*/ 0x00000000,
|
||||
/*082c*/ 0x00000000,
|
||||
/*082d*/ 0x00000000,
|
||||
/*082e*/ 0x00000000,
|
||||
/*082f*/ 0x00000000,
|
||||
/*0830*/ 0x00000000,
|
||||
/*0831*/ 0x00000000,
|
||||
/*0832*/ 0x00000000,
|
||||
/*0833*/ 0x00200000,
|
||||
/*0834*/ 0x08200820,
|
||||
/*0835*/ 0x08200820,
|
||||
/*0836*/ 0x08200820,
|
||||
/*0837*/ 0x08200820,
|
||||
/*0838*/ 0x08200820,
|
||||
/*0839*/ 0x00000820,
|
||||
/*083a*/ 0x03000300,
|
||||
/*083b*/ 0x03000300,
|
||||
/*083c*/ 0x03000300,
|
||||
/*083d*/ 0x03000300,
|
||||
/*083e*/ 0x00000300,
|
||||
/*083f*/ 0x00000000,
|
||||
/*0840*/ 0x00000000,
|
||||
/*0841*/ 0x00000000,
|
||||
/*0842*/ 0x00000000,
|
||||
/*0843*/ 0x00a00000,
|
||||
/*0844*/ 0x00a000a0,
|
||||
/*0845*/ 0x00a000a0,
|
||||
/*0846*/ 0x00a000a0,
|
||||
/*0847*/ 0x00a000a0,
|
||||
/*0848*/ 0x00a000a0,
|
||||
/*0849*/ 0x00a000a0,
|
||||
/*084a*/ 0x00a000a0,
|
||||
/*084b*/ 0x00a000a0,
|
||||
/*084c*/ 0x010900a0,
|
||||
/*084d*/ 0x02000104,
|
||||
/*084e*/ 0x00000000,
|
||||
/*084f*/ 0x00010000,
|
||||
/*0850*/ 0x00000200,
|
||||
/*0851*/ 0x4041a151,
|
||||
/*0852*/ 0xc00141a0,
|
||||
/*0853*/ 0x0e0100c0,
|
||||
/*0854*/ 0x0010000c,
|
||||
/*0855*/ 0x0c064208,
|
||||
/*0856*/ 0x000f0c18,
|
||||
/*0857*/ 0x00e00140,
|
||||
/*0858*/ 0x00000c20
|
||||
};
|
||||
|
||||
static const uint32_t DDR_PHY_ADR_V_REGSET_M3[DDR_PHY_ADR_V_REGSET_NUM_M3] = {
|
||||
/*0a00*/ 0x00000000,
|
||||
/*0a01*/ 0x00000000,
|
||||
/*0a02*/ 0x00000000,
|
||||
/*0a03*/ 0x00000000,
|
||||
/*0a04*/ 0x00000000,
|
||||
/*0a05*/ 0x00000000,
|
||||
/*0a06*/ 0x00000002,
|
||||
/*0a07*/ 0x00000000,
|
||||
/*0a08*/ 0x00000000,
|
||||
/*0a09*/ 0x00000000,
|
||||
/*0a0a*/ 0x00400320,
|
||||
/*0a0b*/ 0x00000040,
|
||||
/*0a0c*/ 0x00dcba98,
|
||||
/*0a0d*/ 0x00000000,
|
||||
/*0a0e*/ 0x00dcba98,
|
||||
/*0a0f*/ 0x01000000,
|
||||
/*0a10*/ 0x00020003,
|
||||
/*0a11*/ 0x00000000,
|
||||
/*0a12*/ 0x00000000,
|
||||
/*0a13*/ 0x00000000,
|
||||
/*0a14*/ 0x0000002a,
|
||||
/*0a15*/ 0x00000015,
|
||||
/*0a16*/ 0x00000015,
|
||||
/*0a17*/ 0x0000002a,
|
||||
/*0a18*/ 0x00000033,
|
||||
/*0a19*/ 0x0000000c,
|
||||
/*0a1a*/ 0x0000000c,
|
||||
/*0a1b*/ 0x00000033,
|
||||
/*0a1c*/ 0x0a418820,
|
||||
/*0a1d*/ 0x003f0000,
|
||||
/*0a1e*/ 0x0000003f,
|
||||
/*0a1f*/ 0x0002c06e,
|
||||
/*0a20*/ 0x02c002c0,
|
||||
/*0a21*/ 0x02c002c0,
|
||||
/*0a22*/ 0x000002c0,
|
||||
/*0a23*/ 0x42080010,
|
||||
/*0a24*/ 0x00000003
|
||||
/*0a00*/ 0x00000000,
|
||||
/*0a01*/ 0x00000000,
|
||||
/*0a02*/ 0x00000000,
|
||||
/*0a03*/ 0x00000000,
|
||||
/*0a04*/ 0x00000000,
|
||||
/*0a05*/ 0x00000000,
|
||||
/*0a06*/ 0x00000002,
|
||||
/*0a07*/ 0x00000000,
|
||||
/*0a08*/ 0x00000000,
|
||||
/*0a09*/ 0x00000000,
|
||||
/*0a0a*/ 0x00400320,
|
||||
/*0a0b*/ 0x00000040,
|
||||
/*0a0c*/ 0x00dcba98,
|
||||
/*0a0d*/ 0x00000000,
|
||||
/*0a0e*/ 0x00dcba98,
|
||||
/*0a0f*/ 0x01000000,
|
||||
/*0a10*/ 0x00020003,
|
||||
/*0a11*/ 0x00000000,
|
||||
/*0a12*/ 0x00000000,
|
||||
/*0a13*/ 0x00000000,
|
||||
/*0a14*/ 0x0000002a,
|
||||
/*0a15*/ 0x00000015,
|
||||
/*0a16*/ 0x00000015,
|
||||
/*0a17*/ 0x0000002a,
|
||||
/*0a18*/ 0x00000033,
|
||||
/*0a19*/ 0x0000000c,
|
||||
/*0a1a*/ 0x0000000c,
|
||||
/*0a1b*/ 0x00000033,
|
||||
/*0a1c*/ 0x0a418820,
|
||||
/*0a1d*/ 0x003f0000,
|
||||
/*0a1e*/ 0x0000003f,
|
||||
/*0a1f*/ 0x0002c06e,
|
||||
/*0a20*/ 0x02c002c0,
|
||||
/*0a21*/ 0x02c002c0,
|
||||
/*0a22*/ 0x000002c0,
|
||||
/*0a23*/ 0x42080010,
|
||||
/*0a24*/ 0x00000003
|
||||
};
|
||||
|
||||
static const uint32_t DDR_PHY_ADR_I_REGSET_M3[DDR_PHY_ADR_I_REGSET_NUM_M3] = {
|
||||
/*0a80*/ 0x04040404,
|
||||
/*0a81*/ 0x00000404,
|
||||
/*0a82*/ 0x00000000,
|
||||
/*0a83*/ 0x00000000,
|
||||
/*0a84*/ 0x00000000,
|
||||
/*0a85*/ 0x00000000,
|
||||
/*0a86*/ 0x00000002,
|
||||
/*0a87*/ 0x00000000,
|
||||
/*0a88*/ 0x00000000,
|
||||
/*0a89*/ 0x00000000,
|
||||
/*0a8a*/ 0x00400320,
|
||||
/*0a8b*/ 0x00000040,
|
||||
/*0a8c*/ 0x00000000,
|
||||
/*0a8d*/ 0x00000000,
|
||||
/*0a8e*/ 0x00000000,
|
||||
/*0a8f*/ 0x01000000,
|
||||
/*0a90*/ 0x00020003,
|
||||
/*0a91*/ 0x00000000,
|
||||
/*0a92*/ 0x00000000,
|
||||
/*0a93*/ 0x00000000,
|
||||
/*0a94*/ 0x0000002a,
|
||||
/*0a95*/ 0x00000015,
|
||||
/*0a96*/ 0x00000015,
|
||||
/*0a97*/ 0x0000002a,
|
||||
/*0a98*/ 0x00000033,
|
||||
/*0a99*/ 0x0000000c,
|
||||
/*0a9a*/ 0x0000000c,
|
||||
/*0a9b*/ 0x00000033,
|
||||
/*0a9c*/ 0x00000000,
|
||||
/*0a9d*/ 0x00000000,
|
||||
/*0a9e*/ 0x00000000,
|
||||
/*0a9f*/ 0x0002c06e,
|
||||
/*0aa0*/ 0x02c002c0,
|
||||
/*0aa1*/ 0x02c002c0,
|
||||
/*0aa2*/ 0x000002c0,
|
||||
/*0aa3*/ 0x42080010,
|
||||
/*0aa4*/ 0x00000003
|
||||
/*0a80*/ 0x04040404,
|
||||
/*0a81*/ 0x00000404,
|
||||
/*0a82*/ 0x00000000,
|
||||
/*0a83*/ 0x00000000,
|
||||
/*0a84*/ 0x00000000,
|
||||
/*0a85*/ 0x00000000,
|
||||
/*0a86*/ 0x00000002,
|
||||
/*0a87*/ 0x00000000,
|
||||
/*0a88*/ 0x00000000,
|
||||
/*0a89*/ 0x00000000,
|
||||
/*0a8a*/ 0x00400320,
|
||||
/*0a8b*/ 0x00000040,
|
||||
/*0a8c*/ 0x00000000,
|
||||
/*0a8d*/ 0x00000000,
|
||||
/*0a8e*/ 0x00000000,
|
||||
/*0a8f*/ 0x01000000,
|
||||
/*0a90*/ 0x00020003,
|
||||
/*0a91*/ 0x00000000,
|
||||
/*0a92*/ 0x00000000,
|
||||
/*0a93*/ 0x00000000,
|
||||
/*0a94*/ 0x0000002a,
|
||||
/*0a95*/ 0x00000015,
|
||||
/*0a96*/ 0x00000015,
|
||||
/*0a97*/ 0x0000002a,
|
||||
/*0a98*/ 0x00000033,
|
||||
/*0a99*/ 0x0000000c,
|
||||
/*0a9a*/ 0x0000000c,
|
||||
/*0a9b*/ 0x00000033,
|
||||
/*0a9c*/ 0x00000000,
|
||||
/*0a9d*/ 0x00000000,
|
||||
/*0a9e*/ 0x00000000,
|
||||
/*0a9f*/ 0x0002c06e,
|
||||
/*0aa0*/ 0x02c002c0,
|
||||
/*0aa1*/ 0x02c002c0,
|
||||
/*0aa2*/ 0x000002c0,
|
||||
/*0aa3*/ 0x42080010,
|
||||
/*0aa4*/ 0x00000003
|
||||
};
|
||||
|
||||
static const uint32_t DDR_PHY_ADR_G_REGSET_M3[DDR_PHY_ADR_G_REGSET_NUM_M3] = {
|
||||
/*0b80*/ 0x00000001,
|
||||
/*0b81*/ 0x00000000,
|
||||
/*0b82*/ 0x00000005,
|
||||
/*0b83*/ 0x04000f00,
|
||||
/*0b84*/ 0x00020080,
|
||||
/*0b85*/ 0x00020055,
|
||||
/*0b86*/ 0x00000000,
|
||||
/*0b87*/ 0x00000000,
|
||||
/*0b88*/ 0x00000000,
|
||||
/*0b89*/ 0x00000050,
|
||||
/*0b8a*/ 0x00000000,
|
||||
/*0b8b*/ 0x01010100,
|
||||
/*0b8c*/ 0x00000600,
|
||||
/*0b8d*/ 0x50640000,
|
||||
/*0b8e*/ 0x01421142,
|
||||
/*0b8f*/ 0x00000142,
|
||||
/*0b90*/ 0x00000000,
|
||||
/*0b91*/ 0x000f1600,
|
||||
/*0b92*/ 0x0f160f16,
|
||||
/*0b93*/ 0x0f160f16,
|
||||
/*0b94*/ 0x00000003,
|
||||
/*0b95*/ 0x0002c000,
|
||||
/*0b96*/ 0x02c002c0,
|
||||
/*0b97*/ 0x000002c0,
|
||||
/*0b98*/ 0x03421342,
|
||||
/*0b99*/ 0x00000342,
|
||||
/*0b9a*/ 0x00000000,
|
||||
/*0b9b*/ 0x00000000,
|
||||
/*0b9c*/ 0x05020000,
|
||||
/*0b9d*/ 0x00000000,
|
||||
/*0b9e*/ 0x00027f6e,
|
||||
/*0b9f*/ 0x047f027f,
|
||||
/*0ba0*/ 0x00027f6e,
|
||||
/*0ba1*/ 0x00047f6e,
|
||||
/*0ba2*/ 0x0003554f,
|
||||
/*0ba3*/ 0x0001554f,
|
||||
/*0ba4*/ 0x0001554f,
|
||||
/*0ba5*/ 0x0001554f,
|
||||
/*0ba6*/ 0x0001554f,
|
||||
/*0ba7*/ 0x00003fee,
|
||||
/*0ba8*/ 0x0001554f,
|
||||
/*0ba9*/ 0x00003fee,
|
||||
/*0baa*/ 0x0001554f,
|
||||
/*0bab*/ 0x00027f6e,
|
||||
/*0bac*/ 0x0001554f,
|
||||
/*0bad*/ 0x00000000,
|
||||
/*0bae*/ 0x00000000,
|
||||
/*0baf*/ 0x00000000,
|
||||
/*0bb0*/ 0x65000000,
|
||||
/*0bb1*/ 0x00000000,
|
||||
/*0bb2*/ 0x00000000,
|
||||
/*0bb3*/ 0x00000201,
|
||||
/*0bb4*/ 0x00000000,
|
||||
/*0bb5*/ 0x00000000,
|
||||
/*0bb6*/ 0x00000000,
|
||||
/*0bb7*/ 0x00000000,
|
||||
/*0bb8*/ 0x00000000,
|
||||
/*0bb9*/ 0x00000000,
|
||||
/*0bba*/ 0x00000000,
|
||||
/*0bbb*/ 0x00000000,
|
||||
/*0bbc*/ 0x06e40000,
|
||||
/*0bbd*/ 0x00000000,
|
||||
/*0bbe*/ 0x00000000,
|
||||
/*0bbf*/ 0x00010000
|
||||
/*0b80*/ 0x00000001,
|
||||
/*0b81*/ 0x00000000,
|
||||
/*0b82*/ 0x00000005,
|
||||
/*0b83*/ 0x04000f00,
|
||||
/*0b84*/ 0x00020080,
|
||||
/*0b85*/ 0x00020055,
|
||||
/*0b86*/ 0x00000000,
|
||||
/*0b87*/ 0x00000000,
|
||||
/*0b88*/ 0x00000000,
|
||||
/*0b89*/ 0x00000050,
|
||||
/*0b8a*/ 0x00000000,
|
||||
/*0b8b*/ 0x01010100,
|
||||
/*0b8c*/ 0x00000600,
|
||||
/*0b8d*/ 0x50640000,
|
||||
/*0b8e*/ 0x01421142,
|
||||
/*0b8f*/ 0x00000142,
|
||||
/*0b90*/ 0x00000000,
|
||||
/*0b91*/ 0x000f1600,
|
||||
/*0b92*/ 0x0f160f16,
|
||||
/*0b93*/ 0x0f160f16,
|
||||
/*0b94*/ 0x00000003,
|
||||
/*0b95*/ 0x0002c000,
|
||||
/*0b96*/ 0x02c002c0,
|
||||
/*0b97*/ 0x000002c0,
|
||||
/*0b98*/ 0x03421342,
|
||||
/*0b99*/ 0x00000342,
|
||||
/*0b9a*/ 0x00000000,
|
||||
/*0b9b*/ 0x00000000,
|
||||
/*0b9c*/ 0x05020000,
|
||||
/*0b9d*/ 0x00000000,
|
||||
/*0b9e*/ 0x00027f6e,
|
||||
/*0b9f*/ 0x047f027f,
|
||||
/*0ba0*/ 0x00027f6e,
|
||||
/*0ba1*/ 0x00047f6e,
|
||||
/*0ba2*/ 0x0003554f,
|
||||
/*0ba3*/ 0x0001554f,
|
||||
/*0ba4*/ 0x0001554f,
|
||||
/*0ba5*/ 0x0001554f,
|
||||
/*0ba6*/ 0x0001554f,
|
||||
/*0ba7*/ 0x00003fee,
|
||||
/*0ba8*/ 0x0001554f,
|
||||
/*0ba9*/ 0x00003fee,
|
||||
/*0baa*/ 0x0001554f,
|
||||
/*0bab*/ 0x00027f6e,
|
||||
/*0bac*/ 0x0001554f,
|
||||
/*0bad*/ 0x00000000,
|
||||
/*0bae*/ 0x00000000,
|
||||
/*0baf*/ 0x00000000,
|
||||
/*0bb0*/ 0x65000000,
|
||||
/*0bb1*/ 0x00000000,
|
||||
/*0bb2*/ 0x00000000,
|
||||
/*0bb3*/ 0x00000201,
|
||||
/*0bb4*/ 0x00000000,
|
||||
/*0bb5*/ 0x00000000,
|
||||
/*0bb6*/ 0x00000000,
|
||||
/*0bb7*/ 0x00000000,
|
||||
/*0bb8*/ 0x00000000,
|
||||
/*0bb9*/ 0x00000000,
|
||||
/*0bba*/ 0x00000000,
|
||||
/*0bbb*/ 0x00000000,
|
||||
/*0bbc*/ 0x06e40000,
|
||||
/*0bbd*/ 0x00000000,
|
||||
/*0bbe*/ 0x00000000,
|
||||
/*0bbf*/ 0x00010000
|
||||
};
|
||||
|
||||
static const uint32_t DDR_PI_REGSET_M3[DDR_PI_REGSET_NUM_M3] = {
|
||||
/*0200*/ 0x00000b00,
|
||||
/*0201*/ 0x00000100,
|
||||
/*0202*/ 0x00000000,
|
||||
/*0203*/ 0x0000ffff,
|
||||
/*0204*/ 0x00000000,
|
||||
/*0205*/ 0x0000ffff,
|
||||
/*0206*/ 0x00000000,
|
||||
/*0207*/ 0x304cffff,
|
||||
/*0208*/ 0x00000200,
|
||||
/*0209*/ 0x00000200,
|
||||
/*020a*/ 0x00000200,
|
||||
/*020b*/ 0x00000200,
|
||||
/*020c*/ 0x0000304c,
|
||||
/*020d*/ 0x00000200,
|
||||
/*020e*/ 0x00000200,
|
||||
/*020f*/ 0x00000200,
|
||||
/*0210*/ 0x00000200,
|
||||
/*0211*/ 0x0000304c,
|
||||
/*0212*/ 0x00000200,
|
||||
/*0213*/ 0x00000200,
|
||||
/*0214*/ 0x00000200,
|
||||
/*0215*/ 0x00000200,
|
||||
/*0216*/ 0x00010000,
|
||||
/*0217*/ 0x00000003,
|
||||
/*0218*/ 0x01000001,
|
||||
/*0219*/ 0x00000000,
|
||||
/*021a*/ 0x00000000,
|
||||
/*021b*/ 0x00000000,
|
||||
/*021c*/ 0x00000000,
|
||||
/*021d*/ 0x00000000,
|
||||
/*021e*/ 0x00000000,
|
||||
/*021f*/ 0x00000000,
|
||||
/*0220*/ 0x00000000,
|
||||
/*0221*/ 0x00000000,
|
||||
/*0222*/ 0x00000000,
|
||||
/*0223*/ 0x00000000,
|
||||
/*0224*/ 0x00000000,
|
||||
/*0225*/ 0x00000000,
|
||||
/*0226*/ 0x00000000,
|
||||
/*0227*/ 0x00000000,
|
||||
/*0228*/ 0x00000000,
|
||||
/*0229*/ 0x0f000101,
|
||||
/*022a*/ 0x08492d25,
|
||||
/*022b*/ 0x0e0c0004,
|
||||
/*022c*/ 0x000e5000,
|
||||
/*022d*/ 0x00000250,
|
||||
/*022e*/ 0x00460003,
|
||||
/*022f*/ 0x182600cf,
|
||||
/*0230*/ 0x182600cf,
|
||||
/*0231*/ 0x00000005,
|
||||
/*0232*/ 0x00000000,
|
||||
/*0233*/ 0x00000000,
|
||||
/*0234*/ 0x00000000,
|
||||
/*0235*/ 0x00000000,
|
||||
/*0236*/ 0x00000000,
|
||||
/*0237*/ 0x00000000,
|
||||
/*0238*/ 0x00000000,
|
||||
/*0239*/ 0x01000000,
|
||||
/*023a*/ 0x00040404,
|
||||
/*023b*/ 0x01280a00,
|
||||
/*023c*/ 0x00000000,
|
||||
/*023d*/ 0x000f0000,
|
||||
/*023e*/ 0x00001803,
|
||||
/*023f*/ 0x00000000,
|
||||
/*0240*/ 0x00000000,
|
||||
/*0241*/ 0x00060002,
|
||||
/*0242*/ 0x00010001,
|
||||
/*0243*/ 0x01000101,
|
||||
/*0244*/ 0x04020201,
|
||||
/*0245*/ 0x00080804,
|
||||
/*0246*/ 0x00000000,
|
||||
/*0247*/ 0x08030000,
|
||||
/*0248*/ 0x15150408,
|
||||
/*0249*/ 0x00000000,
|
||||
/*024a*/ 0x00000000,
|
||||
/*024b*/ 0x00000000,
|
||||
/*024c*/ 0x000f0f00,
|
||||
/*024d*/ 0x0000001e,
|
||||
/*024e*/ 0x00000000,
|
||||
/*024f*/ 0x01000300,
|
||||
/*0250*/ 0x00000000,
|
||||
/*0251*/ 0x00000000,
|
||||
/*0252*/ 0x01000000,
|
||||
/*0253*/ 0x00010101,
|
||||
/*0254*/ 0x000e0e0e,
|
||||
/*0255*/ 0x000c0c0c,
|
||||
/*0256*/ 0x02060601,
|
||||
/*0257*/ 0x00000000,
|
||||
/*0258*/ 0x00000003,
|
||||
/*0259*/ 0x00181703,
|
||||
/*025a*/ 0x00280006,
|
||||
/*025b*/ 0x00280016,
|
||||
/*025c*/ 0x00000016,
|
||||
/*025d*/ 0x00000000,
|
||||
/*025e*/ 0x00000000,
|
||||
/*025f*/ 0x00000000,
|
||||
/*0260*/ 0x140a0000,
|
||||
/*0261*/ 0x0005010a,
|
||||
/*0262*/ 0x03018d03,
|
||||
/*0263*/ 0x000a018d,
|
||||
/*0264*/ 0x00060100,
|
||||
/*0265*/ 0x01000006,
|
||||
/*0266*/ 0x018e018e,
|
||||
/*0267*/ 0x018e0100,
|
||||
/*0268*/ 0x1111018e,
|
||||
/*0269*/ 0x10010204,
|
||||
/*026a*/ 0x09090650,
|
||||
/*026b*/ 0x20110202,
|
||||
/*026c*/ 0x00201000,
|
||||
/*026d*/ 0x00201000,
|
||||
/*026e*/ 0x04041000,
|
||||
/*026f*/ 0x18020100,
|
||||
/*0270*/ 0x00010118,
|
||||
/*0271*/ 0x004b004a,
|
||||
/*0272*/ 0x050f0000,
|
||||
/*0273*/ 0x0c01021e,
|
||||
/*0274*/ 0x34000000,
|
||||
/*0275*/ 0x00000000,
|
||||
/*0276*/ 0x00000000,
|
||||
/*0277*/ 0x00000000,
|
||||
/*0278*/ 0x0000d400,
|
||||
/*0279*/ 0x0031002e,
|
||||
/*027a*/ 0x00111136,
|
||||
/*027b*/ 0x002e00d4,
|
||||
/*027c*/ 0x11360031,
|
||||
/*027d*/ 0x0000d411,
|
||||
/*027e*/ 0x0031002e,
|
||||
/*027f*/ 0x00111136,
|
||||
/*0280*/ 0x002e00d4,
|
||||
/*0281*/ 0x11360031,
|
||||
/*0282*/ 0x0000d411,
|
||||
/*0283*/ 0x0031002e,
|
||||
/*0284*/ 0x00111136,
|
||||
/*0285*/ 0x002e00d4,
|
||||
/*0286*/ 0x11360031,
|
||||
/*0287*/ 0x00d40011,
|
||||
/*0288*/ 0x0031002e,
|
||||
/*0289*/ 0x00111136,
|
||||
/*028a*/ 0x002e00d4,
|
||||
/*028b*/ 0x11360031,
|
||||
/*028c*/ 0x0000d411,
|
||||
/*028d*/ 0x0031002e,
|
||||
/*028e*/ 0x00111136,
|
||||
/*028f*/ 0x002e00d4,
|
||||
/*0290*/ 0x11360031,
|
||||
/*0291*/ 0x0000d411,
|
||||
/*0292*/ 0x0031002e,
|
||||
/*0293*/ 0x00111136,
|
||||
/*0294*/ 0x002e00d4,
|
||||
/*0295*/ 0x11360031,
|
||||
/*0296*/ 0x02000011,
|
||||
/*0297*/ 0x018d018d,
|
||||
/*0298*/ 0x0c08018d,
|
||||
/*0299*/ 0x1f121d22,
|
||||
/*029a*/ 0x4301b344,
|
||||
/*029b*/ 0x10172006,
|
||||
/*029c*/ 0x1d220c10,
|
||||
/*029d*/ 0x00001f12,
|
||||
/*029e*/ 0x4301b344,
|
||||
/*029f*/ 0x10172006,
|
||||
/*02a0*/ 0x1d220c10,
|
||||
/*02a1*/ 0x00001f12,
|
||||
/*02a2*/ 0x4301b344,
|
||||
/*02a3*/ 0x10172006,
|
||||
/*02a4*/ 0x02000210,
|
||||
/*02a5*/ 0x02000200,
|
||||
/*02a6*/ 0x02000200,
|
||||
/*02a7*/ 0x02000200,
|
||||
/*02a8*/ 0x02000200,
|
||||
/*02a9*/ 0x00000000,
|
||||
/*02aa*/ 0x00000000,
|
||||
/*02ab*/ 0x00000000,
|
||||
/*02ac*/ 0x00000000,
|
||||
/*02ad*/ 0x00000000,
|
||||
/*02ae*/ 0x00000000,
|
||||
/*02af*/ 0x00000000,
|
||||
/*02b0*/ 0x00000000,
|
||||
/*02b1*/ 0x00000000,
|
||||
/*02b2*/ 0x00000000,
|
||||
/*02b3*/ 0x00000000,
|
||||
/*02b4*/ 0x00000000,
|
||||
/*02b5*/ 0x00000400,
|
||||
/*02b6*/ 0x15141312,
|
||||
/*02b7*/ 0x11100f0e,
|
||||
/*02b8*/ 0x080b0c0d,
|
||||
/*02b9*/ 0x05040a09,
|
||||
/*02ba*/ 0x01000706,
|
||||
/*02bb*/ 0x00000302,
|
||||
/*02bc*/ 0x01030201,
|
||||
/*02bd*/ 0x00304c00,
|
||||
/*02be*/ 0x0001e2f8,
|
||||
/*02bf*/ 0x0000304c,
|
||||
/*02c0*/ 0x0001e2f8,
|
||||
/*02c1*/ 0x0000304c,
|
||||
/*02c2*/ 0x0001e2f8,
|
||||
/*02c3*/ 0x08000000,
|
||||
/*02c4*/ 0x00000100,
|
||||
/*02c5*/ 0x00000000,
|
||||
/*02c6*/ 0x00000000,
|
||||
/*02c7*/ 0x00000000,
|
||||
/*02c8*/ 0x00000000,
|
||||
/*02c9*/ 0x00000002
|
||||
/*0200*/ 0x00000b00,
|
||||
/*0201*/ 0x00000100,
|
||||
/*0202*/ 0x00000000,
|
||||
/*0203*/ 0x0000ffff,
|
||||
/*0204*/ 0x00000000,
|
||||
/*0205*/ 0x0000ffff,
|
||||
/*0206*/ 0x00000000,
|
||||
/*0207*/ 0x304cffff,
|
||||
/*0208*/ 0x00000200,
|
||||
/*0209*/ 0x00000200,
|
||||
/*020a*/ 0x00000200,
|
||||
/*020b*/ 0x00000200,
|
||||
/*020c*/ 0x0000304c,
|
||||
/*020d*/ 0x00000200,
|
||||
/*020e*/ 0x00000200,
|
||||
/*020f*/ 0x00000200,
|
||||
/*0210*/ 0x00000200,
|
||||
/*0211*/ 0x0000304c,
|
||||
/*0212*/ 0x00000200,
|
||||
/*0213*/ 0x00000200,
|
||||
/*0214*/ 0x00000200,
|
||||
/*0215*/ 0x00000200,
|
||||
/*0216*/ 0x00010000,
|
||||
/*0217*/ 0x00000003,
|
||||
/*0218*/ 0x01000001,
|
||||
/*0219*/ 0x00000000,
|
||||
/*021a*/ 0x00000000,
|
||||
/*021b*/ 0x00000000,
|
||||
/*021c*/ 0x00000000,
|
||||
/*021d*/ 0x00000000,
|
||||
/*021e*/ 0x00000000,
|
||||
/*021f*/ 0x00000000,
|
||||
/*0220*/ 0x00000000,
|
||||
/*0221*/ 0x00000000,
|
||||
/*0222*/ 0x00000000,
|
||||
/*0223*/ 0x00000000,
|
||||
/*0224*/ 0x00000000,
|
||||
/*0225*/ 0x00000000,
|
||||
/*0226*/ 0x00000000,
|
||||
/*0227*/ 0x00000000,
|
||||
/*0228*/ 0x00000000,
|
||||
/*0229*/ 0x0f000101,
|
||||
/*022a*/ 0x08492d25,
|
||||
/*022b*/ 0x0e0c0004,
|
||||
/*022c*/ 0x000e5000,
|
||||
/*022d*/ 0x00000250,
|
||||
/*022e*/ 0x00460003,
|
||||
/*022f*/ 0x182600cf,
|
||||
/*0230*/ 0x182600cf,
|
||||
/*0231*/ 0x00000005,
|
||||
/*0232*/ 0x00000000,
|
||||
/*0233*/ 0x00000000,
|
||||
/*0234*/ 0x00000000,
|
||||
/*0235*/ 0x00000000,
|
||||
/*0236*/ 0x00000000,
|
||||
/*0237*/ 0x00000000,
|
||||
/*0238*/ 0x00000000,
|
||||
/*0239*/ 0x01000000,
|
||||
/*023a*/ 0x00040404,
|
||||
/*023b*/ 0x01280a00,
|
||||
/*023c*/ 0x00000000,
|
||||
/*023d*/ 0x000f0000,
|
||||
/*023e*/ 0x00001803,
|
||||
/*023f*/ 0x00000000,
|
||||
/*0240*/ 0x00000000,
|
||||
/*0241*/ 0x00060002,
|
||||
/*0242*/ 0x00010001,
|
||||
/*0243*/ 0x01000101,
|
||||
/*0244*/ 0x04020201,
|
||||
/*0245*/ 0x00080804,
|
||||
/*0246*/ 0x00000000,
|
||||
/*0247*/ 0x08030000,
|
||||
/*0248*/ 0x15150408,
|
||||
/*0249*/ 0x00000000,
|
||||
/*024a*/ 0x00000000,
|
||||
/*024b*/ 0x00000000,
|
||||
/*024c*/ 0x000f0f00,
|
||||
/*024d*/ 0x0000001e,
|
||||
/*024e*/ 0x00000000,
|
||||
/*024f*/ 0x01000300,
|
||||
/*0250*/ 0x00000000,
|
||||
/*0251*/ 0x00000000,
|
||||
/*0252*/ 0x01000000,
|
||||
/*0253*/ 0x00010101,
|
||||
/*0254*/ 0x000e0e0e,
|
||||
/*0255*/ 0x000c0c0c,
|
||||
/*0256*/ 0x02060601,
|
||||
/*0257*/ 0x00000000,
|
||||
/*0258*/ 0x00000003,
|
||||
/*0259*/ 0x00181703,
|
||||
/*025a*/ 0x00280006,
|
||||
/*025b*/ 0x00280016,
|
||||
/*025c*/ 0x00000016,
|
||||
/*025d*/ 0x00000000,
|
||||
/*025e*/ 0x00000000,
|
||||
/*025f*/ 0x00000000,
|
||||
/*0260*/ 0x140a0000,
|
||||
/*0261*/ 0x0005010a,
|
||||
/*0262*/ 0x03018d03,
|
||||
/*0263*/ 0x000a018d,
|
||||
/*0264*/ 0x00060100,
|
||||
/*0265*/ 0x01000006,
|
||||
/*0266*/ 0x018e018e,
|
||||
/*0267*/ 0x018e0100,
|
||||
/*0268*/ 0x1111018e,
|
||||
/*0269*/ 0x10010204,
|
||||
/*026a*/ 0x09090650,
|
||||
/*026b*/ 0x20110202,
|
||||
/*026c*/ 0x00201000,
|
||||
/*026d*/ 0x00201000,
|
||||
/*026e*/ 0x04041000,
|
||||
/*026f*/ 0x18020100,
|
||||
/*0270*/ 0x00010118,
|
||||
/*0271*/ 0x004b004a,
|
||||
/*0272*/ 0x050f0000,
|
||||
/*0273*/ 0x0c01021e,
|
||||
/*0274*/ 0x34000000,
|
||||
/*0275*/ 0x00000000,
|
||||
/*0276*/ 0x00000000,
|
||||
/*0277*/ 0x00000000,
|
||||
/*0278*/ 0x0000d400,
|
||||
/*0279*/ 0x0031002e,
|
||||
/*027a*/ 0x00111136,
|
||||
/*027b*/ 0x002e00d4,
|
||||
/*027c*/ 0x11360031,
|
||||
/*027d*/ 0x0000d411,
|
||||
/*027e*/ 0x0031002e,
|
||||
/*027f*/ 0x00111136,
|
||||
/*0280*/ 0x002e00d4,
|
||||
/*0281*/ 0x11360031,
|
||||
/*0282*/ 0x0000d411,
|
||||
/*0283*/ 0x0031002e,
|
||||
/*0284*/ 0x00111136,
|
||||
/*0285*/ 0x002e00d4,
|
||||
/*0286*/ 0x11360031,
|
||||
/*0287*/ 0x00d40011,
|
||||
/*0288*/ 0x0031002e,
|
||||
/*0289*/ 0x00111136,
|
||||
/*028a*/ 0x002e00d4,
|
||||
/*028b*/ 0x11360031,
|
||||
/*028c*/ 0x0000d411,
|
||||
/*028d*/ 0x0031002e,
|
||||
/*028e*/ 0x00111136,
|
||||
/*028f*/ 0x002e00d4,
|
||||
/*0290*/ 0x11360031,
|
||||
/*0291*/ 0x0000d411,
|
||||
/*0292*/ 0x0031002e,
|
||||
/*0293*/ 0x00111136,
|
||||
/*0294*/ 0x002e00d4,
|
||||
/*0295*/ 0x11360031,
|
||||
/*0296*/ 0x02000011,
|
||||
/*0297*/ 0x018d018d,
|
||||
/*0298*/ 0x0c08018d,
|
||||
/*0299*/ 0x1f121d22,
|
||||
/*029a*/ 0x4301b344,
|
||||
/*029b*/ 0x10172006,
|
||||
/*029c*/ 0x1d220c10,
|
||||
/*029d*/ 0x00001f12,
|
||||
/*029e*/ 0x4301b344,
|
||||
/*029f*/ 0x10172006,
|
||||
/*02a0*/ 0x1d220c10,
|
||||
/*02a1*/ 0x00001f12,
|
||||
/*02a2*/ 0x4301b344,
|
||||
/*02a3*/ 0x10172006,
|
||||
/*02a4*/ 0x02000210,
|
||||
/*02a5*/ 0x02000200,
|
||||
/*02a6*/ 0x02000200,
|
||||
/*02a7*/ 0x02000200,
|
||||
/*02a8*/ 0x02000200,
|
||||
/*02a9*/ 0x00000000,
|
||||
/*02aa*/ 0x00000000,
|
||||
/*02ab*/ 0x00000000,
|
||||
/*02ac*/ 0x00000000,
|
||||
/*02ad*/ 0x00000000,
|
||||
/*02ae*/ 0x00000000,
|
||||
/*02af*/ 0x00000000,
|
||||
/*02b0*/ 0x00000000,
|
||||
/*02b1*/ 0x00000000,
|
||||
/*02b2*/ 0x00000000,
|
||||
/*02b3*/ 0x00000000,
|
||||
/*02b4*/ 0x00000000,
|
||||
/*02b5*/ 0x00000400,
|
||||
/*02b6*/ 0x15141312,
|
||||
/*02b7*/ 0x11100f0e,
|
||||
/*02b8*/ 0x080b0c0d,
|
||||
/*02b9*/ 0x05040a09,
|
||||
/*02ba*/ 0x01000706,
|
||||
/*02bb*/ 0x00000302,
|
||||
/*02bc*/ 0x01030201,
|
||||
/*02bd*/ 0x00304c00,
|
||||
/*02be*/ 0x0001e2f8,
|
||||
/*02bf*/ 0x0000304c,
|
||||
/*02c0*/ 0x0001e2f8,
|
||||
/*02c1*/ 0x0000304c,
|
||||
/*02c2*/ 0x0001e2f8,
|
||||
/*02c3*/ 0x08000000,
|
||||
/*02c4*/ 0x00000100,
|
||||
/*02c5*/ 0x00000000,
|
||||
/*02c6*/ 0x00000000,
|
||||
/*02c7*/ 0x00000000,
|
||||
/*02c8*/ 0x00000000,
|
||||
/*02c9*/ 0x00000002
|
||||
};
|
||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,257 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2019, Renesas Electronics Corporation
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef BOOT_INIT_DRAM_REGDEF_H_
|
||||
#define BOOT_INIT_DRAM_REGDEF_H_
|
||||
|
||||
/* DBSC registers */
|
||||
#define DBSC_DBSYSCONF0 0xE6790000U
|
||||
#define DBSC_DBSYSCONF1 0xE6790004U
|
||||
#define DBSC_DBPHYCONF0 0xE6790010U
|
||||
#define DBSC_DBKIND 0xE6790020U
|
||||
#define DBSC_DBMEMCONF(ch, cs) (0xE6790030U + 0x10U * (ch) + 0x04U * (cs))
|
||||
#define DBSC_DBMEMCONF_0_0 0xE6790030U
|
||||
#define DBSC_DBMEMCONF_0_1 0xE6790034U
|
||||
#define DBSC_DBMEMCONF_0_2 0xE6790038U
|
||||
#define DBSC_DBMEMCONF_0_3 0xE679003CU
|
||||
#define DBSC_DBMEMCONF_1_2 0xE6790048U
|
||||
#define DBSC_DBMEMCONF_1_3 0xE679004CU
|
||||
#define DBSC_DBMEMCONF_1_0 0xE6790040U
|
||||
#define DBSC_DBMEMCONF_1_1 0xE6790044U
|
||||
#define DBSC_DBMEMCONF_2_0 0xE6790050U
|
||||
#define DBSC_DBMEMCONF_2_1 0xE6790054U
|
||||
#define DBSC_DBMEMCONF_2_2 0xE6790058U
|
||||
#define DBSC_DBMEMCONF_2_3 0xE679005CU
|
||||
#define DBSC_DBMEMCONF_3_0 0xE6790060U
|
||||
#define DBSC_DBMEMCONF_3_1 0xE6790064U
|
||||
#define DBSC_DBMEMCONF_3_2 0xE6790068U
|
||||
#define DBSC_DBMEMCONF_3_3 0xE679006CU
|
||||
#define DBSC_DBSYSCNT0 0xE6790100U
|
||||
#define DBSC_DBSVCR1 0xE6790104U
|
||||
#define DBSC_DBSTATE0 0xE6790108U
|
||||
#define DBSC_DBSTATE1 0xE679010CU
|
||||
#define DBSC_DBINTEN 0xE6790180U
|
||||
#define DBSC_DBINTSTAT0 0xE6790184U
|
||||
#define DBSC_DBACEN 0xE6790200U
|
||||
#define DBSC_DBRFEN 0xE6790204U
|
||||
#define DBSC_DBCMD 0xE6790208U
|
||||
#define DBSC_DBWAIT 0xE6790210U
|
||||
#define DBSC_DBSYSCTRL0 0xE6790280U
|
||||
#define DBSC_DBTR(x) (0xE6790300U + 0x04U * (x))
|
||||
#define DBSC_DBTR0 0xE6790300U
|
||||
#define DBSC_DBTR1 0xE6790304U
|
||||
#define DBSC_DBTR2 0xE6790308U
|
||||
#define DBSC_DBTR3 0xE679030CU
|
||||
#define DBSC_DBTR4 0xE6790310U
|
||||
#define DBSC_DBTR5 0xE6790314U
|
||||
#define DBSC_DBTR6 0xE6790318U
|
||||
#define DBSC_DBTR7 0xE679031CU
|
||||
#define DBSC_DBTR8 0xE6790320U
|
||||
#define DBSC_DBTR9 0xE6790324U
|
||||
#define DBSC_DBTR10 0xE6790328U
|
||||
#define DBSC_DBTR11 0xE679032CU
|
||||
#define DBSC_DBTR12 0xE6790330U
|
||||
#define DBSC_DBTR13 0xE6790334U
|
||||
#define DBSC_DBTR14 0xE6790338U
|
||||
#define DBSC_DBTR15 0xE679033CU
|
||||
#define DBSC_DBTR16 0xE6790340U
|
||||
#define DBSC_DBTR17 0xE6790344U
|
||||
#define DBSC_DBTR18 0xE6790348U
|
||||
#define DBSC_DBTR19 0xE679034CU
|
||||
#define DBSC_DBTR20 0xE6790350U
|
||||
#define DBSC_DBTR21 0xE6790354U
|
||||
#define DBSC_DBTR22 0xE6790358U
|
||||
#define DBSC_DBTR23 0xE679035CU
|
||||
#define DBSC_DBTR24 0xE6790360U
|
||||
#define DBSC_DBTR25 0xE6790364U
|
||||
#define DBSC_DBTR26 0xE6790368U
|
||||
#define DBSC_DBBL 0xE6790400U
|
||||
#define DBSC_DBRFCNF1 0xE6790414U
|
||||
#define DBSC_DBRFCNF2 0xE6790418U
|
||||
#define DBSC_DBTSPCNF 0xE6790420U
|
||||
#define DBSC_DBCALCNF 0xE6790424U
|
||||
#define DBSC_DBRNK(x) (0xE6790430U + 0x04U * (x))
|
||||
#define DBSC_DBRNK2 0xE6790438U
|
||||
#define DBSC_DBRNK3 0xE679043CU
|
||||
#define DBSC_DBRNK4 0xE6790440U
|
||||
#define DBSC_DBRNK5 0xE6790444U
|
||||
#define DBSC_DBPDNCNF 0xE6790450U
|
||||
#define DBSC_DBODT(x) (0xE6790460U + 0x04U * (x))
|
||||
#define DBSC_DBODT0 0xE6790460U
|
||||
#define DBSC_DBODT1 0xE6790464U
|
||||
#define DBSC_DBODT2 0xE6790468U
|
||||
#define DBSC_DBODT3 0xE679046CU
|
||||
#define DBSC_DBODT4 0xE6790470U
|
||||
#define DBSC_DBODT5 0xE6790474U
|
||||
#define DBSC_DBODT6 0xE6790478U
|
||||
#define DBSC_DBODT7 0xE679047CU
|
||||
#define DBSC_DBADJ0 0xE6790500U
|
||||
#define DBSC_DBDBICNT 0xE6790518U
|
||||
#define DBSC_DBDFIPMSTRCNF 0xE6790520U
|
||||
#define DBSC_DBDFICUPDCNF 0xE679052CU
|
||||
#define DBSC_DBDFISTAT(ch) (0xE6790600U + 0x40U * (ch))
|
||||
#define DBSC_DBDFISTAT_0 0xE6790600U
|
||||
#define DBSC_DBDFISTAT_1 0xE6790640U
|
||||
#define DBSC_DBDFISTAT_2 0xE6790680U
|
||||
#define DBSC_DBDFISTAT_3 0xE67906C0U
|
||||
#define DBSC_DBDFICNT(ch) (0xE6790604U + 0x40U * (ch))
|
||||
#define DBSC_DBDFICNT_0 0xE6790604U
|
||||
#define DBSC_DBDFICNT_1 0xE6790644U
|
||||
#define DBSC_DBDFICNT_2 0xE6790684U
|
||||
#define DBSC_DBDFICNT_3 0xE67906C4U
|
||||
#define DBSC_DBPDCNT0(ch) (0xE6790610U + 0x40U * (ch))
|
||||
#define DBSC_DBPDCNT0_0 0xE6790610U
|
||||
#define DBSC_DBPDCNT0_1 0xE6790650U
|
||||
#define DBSC_DBPDCNT0_2 0xE6790690U
|
||||
#define DBSC_DBPDCNT0_3 0xE67906D0U
|
||||
#define DBSC_DBPDCNT1(ch) (0xE6790614U + 0x40U * (ch))
|
||||
#define DBSC_DBPDCNT1_0 0xE6790614U
|
||||
#define DBSC_DBPDCNT1_1 0xE6790654U
|
||||
#define DBSC_DBPDCNT1_2 0xE6790694U
|
||||
#define DBSC_DBPDCNT1_3 0xE67906D4U
|
||||
#define DBSC_DBPDCNT2(ch) (0xE6790618U + 0x40U * (ch))
|
||||
#define DBSC_DBPDCNT2_0 0xE6790618U
|
||||
#define DBSC_DBPDCNT2_1 0xE6790658U
|
||||
#define DBSC_DBPDCNT2_2 0xE6790698U
|
||||
#define DBSC_DBPDCNT2_3 0xE67906D8U
|
||||
#define DBSC_DBPDCNT3(ch) (0xE679061CU + 0x40U * (ch))
|
||||
#define DBSC_DBPDCNT3_0 0xE679061CU
|
||||
#define DBSC_DBPDCNT3_1 0xE679065CU
|
||||
#define DBSC_DBPDCNT3_2 0xE679069CU
|
||||
#define DBSC_DBPDCNT3_3 0xE67906DCU
|
||||
#define DBSC_DBPDLK(ch) (0xE6790620U + 0x40U * (ch))
|
||||
#define DBSC_DBPDLK_0 0xE6790620U
|
||||
#define DBSC_DBPDLK_1 0xE6790660U
|
||||
#define DBSC_DBPDLK_2 0xE67906a0U
|
||||
#define DBSC_DBPDLK_3 0xE67906e0U
|
||||
#define DBSC_DBPDRGA(ch) (0xE6790624U + 0x40U * (ch))
|
||||
#define DBSC_DBPDRGD(ch) (0xE6790628U + 0x40U * (ch))
|
||||
#define DBSC_DBPDRGA_0 0xE6790624U
|
||||
#define DBSC_DBPDRGD_0 0xE6790628U
|
||||
#define DBSC_DBPDRGA_1 0xE6790664U
|
||||
#define DBSC_DBPDRGD_1 0xE6790668U
|
||||
#define DBSC_DBPDRGA_2 0xE67906A4U
|
||||
#define DBSC_DBPDRGD_2 0xE67906A8U
|
||||
#define DBSC_DBPDRGA_3 0xE67906E4U
|
||||
#define DBSC_DBPDRGD_3 0xE67906E8U
|
||||
#define DBSC_DBPDSTAT(ch) (0xE6790630U + 0x40U * (ch))
|
||||
#define DBSC_DBPDSTAT_0 0xE6790630U
|
||||
#define DBSC_DBPDSTAT_1 0xE6790670U
|
||||
#define DBSC_DBPDSTAT_2 0xE67906B0U
|
||||
#define DBSC_DBPDSTAT_3 0xE67906F0U
|
||||
#define DBSC_DBBUS0CNF0 0xE6790800U
|
||||
#define DBSC_DBBUS0CNF1 0xE6790804U
|
||||
#define DBSC_DBCAM0CNF1 0xE6790904U
|
||||
#define DBSC_DBCAM0CNF2 0xE6790908U
|
||||
#define DBSC_DBCAM0CNF3 0xE679090CU
|
||||
#define DBSC_DBBSWAP 0xE67909F0U
|
||||
#define DBSC_DBBCAMDIS 0xE67909FCU
|
||||
#define DBSC_DBSCHCNT0 0xE6791000U
|
||||
#define DBSC_DBSCHCNT1 0xE6791004U
|
||||
#define DBSC_DBSCHSZ0 0xE6791010U
|
||||
#define DBSC_DBSCHRW0 0xE6791020U
|
||||
#define DBSC_DBSCHRW1 0xE6791024U
|
||||
#define DBSC_DBSCHQOS_0(x) (0xE6791030U + 0x10U * (x))
|
||||
#define DBSC_DBSCHQOS_1(x) (0xE6791034U + 0x10U * (x))
|
||||
#define DBSC_DBSCHQOS_2(x) (0xE6791038U + 0x10U * (x))
|
||||
#define DBSC_DBSCHQOS_3(x) (0xE679103CU + 0x10U * (x))
|
||||
#define DBSC_DBSCHQOS00 0xE6791030U
|
||||
#define DBSC_DBSCHQOS01 0xE6791034U
|
||||
#define DBSC_DBSCHQOS02 0xE6791038U
|
||||
#define DBSC_DBSCHQOS03 0xE679103CU
|
||||
#define DBSC_DBSCHQOS10 0xE6791040U
|
||||
#define DBSC_DBSCHQOS11 0xE6791044U
|
||||
#define DBSC_DBSCHQOS12 0xE6791048U
|
||||
#define DBSC_DBSCHQOS13 0xE679104CU
|
||||
#define DBSC_DBSCHQOS20 0xE6791050U
|
||||
#define DBSC_DBSCHQOS21 0xE6791054U
|
||||
#define DBSC_DBSCHQOS22 0xE6791058U
|
||||
#define DBSC_DBSCHQOS23 0xE679105CU
|
||||
#define DBSC_DBSCHQOS30 0xE6791060U
|
||||
#define DBSC_DBSCHQOS31 0xE6791064U
|
||||
#define DBSC_DBSCHQOS32 0xE6791068U
|
||||
#define DBSC_DBSCHQOS33 0xE679106CU
|
||||
#define DBSC_DBSCHQOS40 0xE6791070U
|
||||
#define DBSC_DBSCHQOS41 0xE6791074U
|
||||
#define DBSC_DBSCHQOS42 0xE6791078U
|
||||
#define DBSC_DBSCHQOS43 0xE679107CU
|
||||
#define DBSC_DBSCHQOS50 0xE6791080U
|
||||
#define DBSC_DBSCHQOS51 0xE6791084U
|
||||
#define DBSC_DBSCHQOS52 0xE6791088U
|
||||
#define DBSC_DBSCHQOS53 0xE679108CU
|
||||
#define DBSC_DBSCHQOS60 0xE6791090U
|
||||
#define DBSC_DBSCHQOS61 0xE6791094U
|
||||
#define DBSC_DBSCHQOS62 0xE6791098U
|
||||
#define DBSC_DBSCHQOS63 0xE679109CU
|
||||
#define DBSC_DBSCHQOS70 0xE67910A0U
|
||||
#define DBSC_DBSCHQOS71 0xE67910A4U
|
||||
#define DBSC_DBSCHQOS72 0xE67910A8U
|
||||
#define DBSC_DBSCHQOS73 0xE67910ACU
|
||||
#define DBSC_DBSCHQOS80 0xE67910B0U
|
||||
#define DBSC_DBSCHQOS81 0xE67910B4U
|
||||
#define DBSC_DBSCHQOS82 0xE67910B8U
|
||||
#define DBSC_DBSCHQOS83 0xE67910BCU
|
||||
#define DBSC_DBSCHQOS90 0xE67910C0U
|
||||
#define DBSC_DBSCHQOS91 0xE67910C4U
|
||||
#define DBSC_DBSCHQOS92 0xE67910C8U
|
||||
#define DBSC_DBSCHQOS93 0xE67910CCU
|
||||
#define DBSC_DBSCHQOS100 0xE67910D0U
|
||||
#define DBSC_DBSCHQOS101 0xE67910D4U
|
||||
#define DBSC_DBSCHQOS102 0xE67910D8U
|
||||
#define DBSC_DBSCHQOS103 0xE67910DCU
|
||||
#define DBSC_DBSCHQOS110 0xE67910E0U
|
||||
#define DBSC_DBSCHQOS111 0xE67910E4U
|
||||
#define DBSC_DBSCHQOS112 0xE67910E8U
|
||||
#define DBSC_DBSCHQOS113 0xE67910ECU
|
||||
#define DBSC_DBSCHQOS120 0xE67910F0U
|
||||
#define DBSC_DBSCHQOS121 0xE67910F4U
|
||||
#define DBSC_DBSCHQOS122 0xE67910F8U
|
||||
#define DBSC_DBSCHQOS123 0xE67910FCU
|
||||
#define DBSC_DBSCHQOS130 0xE6791100U
|
||||
#define DBSC_DBSCHQOS131 0xE6791104U
|
||||
#define DBSC_DBSCHQOS132 0xE6791108U
|
||||
#define DBSC_DBSCHQOS133 0xE679110CU
|
||||
#define DBSC_DBSCHQOS140 0xE6791110U
|
||||
#define DBSC_DBSCHQOS141 0xE6791114U
|
||||
#define DBSC_DBSCHQOS142 0xE6791118U
|
||||
#define DBSC_DBSCHQOS143 0xE679111CU
|
||||
#define DBSC_DBSCHQOS150 0xE6791120U
|
||||
#define DBSC_DBSCHQOS151 0xE6791124U
|
||||
#define DBSC_DBSCHQOS152 0xE6791128U
|
||||
#define DBSC_DBSCHQOS153 0xE679112CU
|
||||
#define DBSC_DBSCTR0 0xE6791700U
|
||||
#define DBSC_DBSCTR1 0xE6791708U
|
||||
#define DBSC_DBSCHRW2 0xE679170CU
|
||||
#define DBSC_SCFCTST01(x) (0xE6791700U + 0x08U * (x))
|
||||
#define DBSC_SCFCTST0 0xE6791700U
|
||||
#define DBSC_SCFCTST1 0xE6791708U
|
||||
#define DBSC_SCFCTST2 0xE679170CU
|
||||
#define DBSC_DBMRRDR(chab) (0xE6791800U + 0x04U * (chab))
|
||||
#define DBSC_DBMRRDR_0 0xE6791800U
|
||||
#define DBSC_DBMRRDR_1 0xE6791804U
|
||||
#define DBSC_DBMRRDR_2 0xE6791808U
|
||||
#define DBSC_DBMRRDR_3 0xE679180CU
|
||||
#define DBSC_DBMRRDR_4 0xE6791810U
|
||||
#define DBSC_DBMRRDR_5 0xE6791814U
|
||||
#define DBSC_DBMRRDR_6 0xE6791818U
|
||||
#define DBSC_DBMRRDR_7 0xE679181CU
|
||||
#define DBSC_DBMEMSWAPCONF0 0xE6792000U
|
||||
|
||||
/* CPG registers */
|
||||
#define CPG_BASE 0xE6150000U
|
||||
#define CPG_FRQCRB (CPG_BASE + 0x0004U)
|
||||
#define CPG_PLLECR (CPG_BASE + 0x00D0U)
|
||||
#define CPG_MSTPSR5 (CPG_BASE + 0x003CU)
|
||||
#define CPG_SRCR4 (CPG_BASE + 0x00BCU)
|
||||
#define CPG_PLL3CR (CPG_BASE + 0x00DCU)
|
||||
#define CPG_ZB3CKCR (CPG_BASE + 0x0380U)
|
||||
#define CPG_FRQCRD (CPG_BASE + 0x00E4U)
|
||||
#define CPG_SMSTPCR5 (CPG_BASE + 0x0144U)
|
||||
#define CPG_CPGWPR (CPG_BASE + 0x0900U)
|
||||
#define CPG_SRSTCLR4 (CPG_BASE + 0x0950U)
|
||||
|
||||
#endif /* BOOT_INIT_DRAM_REGDEF_H_*/
|
|
@ -12,38 +12,30 @@
|
|||
|
||||
#if RCAR_SYSTEM_SUSPEND
|
||||
/* Local defines */
|
||||
#define DRAM_BACKUP_GPIO_USE (0)
|
||||
#define DRAM_BACKUP_GPIO_USE 0
|
||||
#include "iic_dvfs.h"
|
||||
#if PMIC_ROHM_BD9571
|
||||
#define PMIC_SLAVE_ADDR (0x30U)
|
||||
#define PMIC_BKUP_MODE_CNT (0x20U)
|
||||
#define PMIC_QLLM_CNT (0x27U)
|
||||
#define BIT_BKUP_CTRL_OUT ((uint8_t)(1U << 4U))
|
||||
#define BIT_QLLM_DDR0_EN ((uint8_t)(1U << 0U))
|
||||
#define BIT_QLLM_DDR1_EN ((uint8_t)(1U << 1U))
|
||||
#define PMIC_SLAVE_ADDR 0x30U
|
||||
#define PMIC_BKUP_MODE_CNT 0x20U
|
||||
#define PMIC_QLLM_CNT 0x27U
|
||||
#define BIT_BKUP_CTRL_OUT BIT(4)
|
||||
#define BIT_QLLM_DDR0_EN BIT(0)
|
||||
#define BIT_QLLM_DDR1_EN BIT(1)
|
||||
#endif
|
||||
|
||||
#define GPIO_OUTDT1 (0xE6051008U)
|
||||
#define GPIO_OUTDT3 (0xE6053008U)
|
||||
#define GPIO_INDT3 (0xE605300CU)
|
||||
#define GPIO_OUTDT6 (0xE6055408U)
|
||||
#define GPIO_BKUP_REQB_SHIFT_SALVATOR 9U /* GP1_9 (BKUP_REQB) */
|
||||
#define GPIO_BKUP_TRG_SHIFT_SALVATOR 8U /* GP1_8 (BKUP_TRG) */
|
||||
#define GPIO_BKUP_REQB_SHIFT_EBISU 14U /* GP6_14(BKUP_REQB) */
|
||||
#define GPIO_BKUP_TRG_SHIFT_EBISU 13U /* GP6_13(BKUP_TRG) */
|
||||
#define GPIO_BKUP_REQB_SHIFT_CONDOR 1U /* GP3_1 (BKUP_REQB) */
|
||||
#define GPIO_BKUP_TRG_SHIFT_CONDOR 0U /* GP3_0 (BKUP_TRG) */
|
||||
|
||||
#if DRAM_BACKUP_GPIO_USE == 1
|
||||
#define GPIO_BKUP_REQB_SHIFT_SALVATOR (9U) /* GP1_9 (BKUP_REQB) */
|
||||
#define GPIO_BKUP_REQB_SHIFT_EBISU (14U) /* GP6_14(BKUP_REQB) */
|
||||
#define GPIO_BKUP_REQB_SHIFT_CONDOR (1U) /* GP3_1 (BKUP_REQB) */
|
||||
#endif
|
||||
#define GPIO_BKUP_TRG_SHIFT_SALVATOR (8U) /* GP1_8 (BKUP_TRG) */
|
||||
#define GPIO_BKUP_TRG_SHIFT_EBISU (13U) /* GP6_13(BKUP_TRG) */
|
||||
#define GPIO_BKUP_TRG_SHIFT_CONDOR (0U) /* GP3_0 (BKUP_TRG) */
|
||||
|
||||
#define DRAM_BKUP_TRG_LOOP_CNT (1000U)
|
||||
#define DRAM_BKUP_TRG_LOOP_CNT 1000U
|
||||
#endif
|
||||
|
||||
void rcar_dram_get_boot_status(uint32_t * status)
|
||||
void rcar_dram_get_boot_status(uint32_t *status)
|
||||
{
|
||||
#if RCAR_SYSTEM_SUSPEND
|
||||
|
||||
uint32_t reg_data;
|
||||
uint32_t product;
|
||||
uint32_t shift;
|
||||
|
@ -62,11 +54,10 @@ void rcar_dram_get_boot_status(uint32_t * status)
|
|||
}
|
||||
|
||||
reg_data = mmio_read_32(gpio);
|
||||
if (0U != (reg_data & ((uint32_t)1U << shift))) {
|
||||
if (reg_data & BIT(shift))
|
||||
*status = DRAM_BOOT_STATUS_WARM;
|
||||
} else {
|
||||
else
|
||||
*status = DRAM_BOOT_STATUS_COLD;
|
||||
}
|
||||
#else /* RCAR_SYSTEM_SUSPEND */
|
||||
*status = DRAM_BOOT_STATUS_COLD;
|
||||
#endif /* RCAR_SYSTEM_SUSPEND */
|
||||
|
@ -116,55 +107,55 @@ int32_t rcar_dram_update_boot_status(uint32_t status)
|
|||
}
|
||||
|
||||
if (status == DRAM_BOOT_STATUS_WARM) {
|
||||
#if DRAM_BACKUP_GPIO_USE==1
|
||||
mmio_setbits_32(outd, 1U << reqb);
|
||||
#if DRAM_BACKUP_GPIO_USE == 1
|
||||
mmio_setbits_32(outd, BIT(reqb));
|
||||
#else
|
||||
#if PMIC_ROHM_BD9571
|
||||
/* Set BKUP_CRTL_OUT=High (BKUP mode cnt register) */
|
||||
i2c_dvfs_ret = rcar_iic_dvfs_receive(PMIC_SLAVE_ADDR,
|
||||
PMIC_BKUP_MODE_CNT, &bkup_mode_cnt);
|
||||
if (0 != i2c_dvfs_ret) {
|
||||
PMIC_BKUP_MODE_CNT,
|
||||
&bkup_mode_cnt);
|
||||
if (i2c_dvfs_ret) {
|
||||
ERROR("BKUP mode cnt READ ERROR.\n");
|
||||
ret = DRAM_UPDATE_STATUS_ERR;
|
||||
} else {
|
||||
bkup_mode_cnt &= (uint8_t)~BIT_BKUP_CTRL_OUT;
|
||||
i2c_dvfs_ret = rcar_iic_dvfs_send(PMIC_SLAVE_ADDR,
|
||||
PMIC_BKUP_MODE_CNT, bkup_mode_cnt);
|
||||
if (0 != i2c_dvfs_ret) {
|
||||
ERROR("BKUP mode cnt WRITE ERROR. "
|
||||
"value = %d\n", bkup_mode_cnt);
|
||||
PMIC_BKUP_MODE_CNT,
|
||||
bkup_mode_cnt);
|
||||
if (i2c_dvfs_ret) {
|
||||
ERROR("BKUP mode cnt WRITE ERROR. value = %d\n",
|
||||
bkup_mode_cnt);
|
||||
ret = DRAM_UPDATE_STATUS_ERR;
|
||||
}
|
||||
}
|
||||
#endif /* PMIC_ROHM_BD9571 */
|
||||
#endif /* DRAM_BACKUP_GPIO_USE==1 */
|
||||
#endif /* DRAM_BACKUP_GPIO_USE == 1 */
|
||||
/* Wait BKUP_TRG=Low */
|
||||
loop_count = DRAM_BKUP_TRG_LOOP_CNT;
|
||||
while (0U < loop_count) {
|
||||
while (loop_count > 0) {
|
||||
reg_data = mmio_read_32(gpio);
|
||||
if ((reg_data &
|
||||
((uint32_t)1U << trg)) == 0U) {
|
||||
if (!(reg_data & BIT(trg)))
|
||||
break;
|
||||
}
|
||||
loop_count--;
|
||||
}
|
||||
if (0U == loop_count) {
|
||||
ERROR( "\nWarm booting...\n" \
|
||||
" The potential of BKUP_TRG did not switch " \
|
||||
"to Low.\n If you expect the operation of " \
|
||||
"cold boot,\n check the board configuration" \
|
||||
" (ex, Dip-SW) and/or the H/W failure.\n");
|
||||
|
||||
if (!loop_count) {
|
||||
ERROR("\nWarm booting...\n"
|
||||
" The potential of BKUP_TRG did not switch to Low.\n"
|
||||
" If you expect the operation of cold boot,\n"
|
||||
" check the board configuration (ex, Dip-SW) and/or the H/W failure.\n");
|
||||
ret = DRAM_UPDATE_STATUS_ERR;
|
||||
}
|
||||
}
|
||||
#if PMIC_ROHM_BD9571
|
||||
if(0 == ret) {
|
||||
qllm_cnt = (BIT_QLLM_DDR0_EN | BIT_QLLM_DDR1_EN);
|
||||
if (!ret) {
|
||||
qllm_cnt = BIT_QLLM_DDR0_EN | BIT_QLLM_DDR1_EN;
|
||||
i2c_dvfs_ret = rcar_iic_dvfs_send(PMIC_SLAVE_ADDR,
|
||||
PMIC_QLLM_CNT, qllm_cnt);
|
||||
if (0 != i2c_dvfs_ret) {
|
||||
ERROR("QLLM cnt WRITE ERROR. "
|
||||
"value = %d\n", qllm_cnt);
|
||||
PMIC_QLLM_CNT,
|
||||
qllm_cnt);
|
||||
if (i2c_dvfs_ret) {
|
||||
ERROR("QLLM cnt WRITE ERROR. value = %d\n", qllm_cnt);
|
||||
ret = DRAM_UPDATE_STATUS_ERR;
|
||||
}
|
||||
}
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
|
||||
* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
@ -7,11 +7,11 @@
|
|||
#ifndef DRAM_SUB_FUNC_H
|
||||
#define DRAM_SUB_FUNC_H
|
||||
|
||||
#define DRAM_UPDATE_STATUS_ERR (-1)
|
||||
#define DRAM_BOOT_STATUS_COLD (0)
|
||||
#define DRAM_BOOT_STATUS_WARM (1)
|
||||
#define DRAM_UPDATE_STATUS_ERR -1
|
||||
#define DRAM_BOOT_STATUS_COLD 0
|
||||
#define DRAM_BOOT_STATUS_WARM 1
|
||||
|
||||
int32_t rcar_dram_update_boot_status(uint32_t status);
|
||||
void rcar_dram_get_boot_status(uint32_t * status);
|
||||
void rcar_dram_get_boot_status(uint32_t *status);
|
||||
|
||||
#endif /* DRAM_SUB_FUNC_H */
|
||||
|
|
|
@ -221,9 +221,11 @@
|
|||
#define CPG_PLL0CR (CPG_BASE + 0x00D8U)
|
||||
#define CPG_PLL2CR (CPG_BASE + 0x002CU)
|
||||
#define CPG_PLL4CR (CPG_BASE + 0x01F4U)
|
||||
#define CPG_CPGWPCR (CPG_BASE + 0x0904U)
|
||||
/* RST Registers */
|
||||
#define RST_BASE (0xE6160000U)
|
||||
#define RST_WDTRSTCR (RST_BASE + 0x0054U)
|
||||
#define RST_MODEMR (RST_BASE + 0x0060U)
|
||||
#define WDTRSTCR_PASSWORD (0xA55A0000U)
|
||||
#define WDTRSTCR_RWDT_RSTMSK ((uint32_t)1U << 0U)
|
||||
/* MFIS Registers */
|
||||
|
@ -267,11 +269,15 @@
|
|||
#define MIDR_CA57 (0x0D07U << MIDR_PN_SHIFT)
|
||||
#define MIDR_CA53 (0x0D03U << MIDR_PN_SHIFT)
|
||||
/* for SuspendToRAM */
|
||||
#define GPIO_BASE (0xE6050000U)
|
||||
#define GPIO_INDT1 (GPIO_BASE + 0x100CU)
|
||||
#define GPIO_BASE (0xE6050000U)
|
||||
#define GPIO_INDT1 (GPIO_BASE + 0x100CU)
|
||||
#define GPIO_INDT3 (GPIO_BASE + 0x300CU)
|
||||
#define GPIO_INDT6 (GPIO_BASE + 0x540CU)
|
||||
#define RCAR_COLD_BOOT (0x00U)
|
||||
#define RCAR_WARM_BOOT (0x01U)
|
||||
#define GPIO_OUTDT1 (GPIO_BASE + 0x1008U)
|
||||
#define GPIO_OUTDT3 (GPIO_BASE + 0x3008U)
|
||||
#define GPIO_OUTDT6 (GPIO_BASE + 0x5408U)
|
||||
#define RCAR_COLD_BOOT (0x00U)
|
||||
#define RCAR_WARM_BOOT (0x01U)
|
||||
#if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR
|
||||
#define KEEP10_MAGIC (0x55U)
|
||||
#endif
|
||||
|
|
Loading…
Reference in New Issue