Merge pull request #1272 from dp-arm/dp/extensions
Refactor SPE/SVE code and fix some bugs in AMUv1 on AArch32
This commit is contained in:
davidcunado-arm
GitHub
commit
f461da2a3e
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -7,6 +7,7 @@
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#ifndef __SPE_H__
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#define __SPE_H__
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int spe_supported(void);
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void spe_enable(int el2_unused);
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void spe_disable(void);
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -7,6 +7,7 @@
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#ifndef __SVE_H__
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#define __SVE_H__
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int sve_supported(void);
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void sve_enable(int el2_unused);
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#endif /* __SVE_H__ */
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@ -30,7 +30,7 @@ int amu_supported(void)
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void amu_enable(int el2_unused)
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{
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if (!amu_supported())
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if (amu_supported() == 0)
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return;
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if (el2_unused) {
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@ -54,7 +54,7 @@ void amu_enable(int el2_unused)
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/* Read the group 0 counter identified by the given `idx`. */
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uint64_t amu_group0_cnt_read(int idx)
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{
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assert(amu_supported());
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assert(amu_supported() != 0);
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assert(idx >= 0 && idx < AMU_GROUP0_NR_COUNTERS);
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return amu_group0_cnt_read_internal(idx);
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@ -63,7 +63,7 @@ uint64_t amu_group0_cnt_read(int idx)
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/* Write the group 0 counter identified by the given `idx` with `val`. */
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void amu_group0_cnt_write(int idx, uint64_t val)
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{
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assert(amu_supported());
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assert(amu_supported() != 0);
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assert(idx >= 0 && idx < AMU_GROUP0_NR_COUNTERS);
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amu_group0_cnt_write_internal(idx, val);
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@ -73,7 +73,7 @@ void amu_group0_cnt_write(int idx, uint64_t val)
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/* Read the group 1 counter identified by the given `idx`. */
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uint64_t amu_group1_cnt_read(int idx)
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{
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assert(amu_supported());
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assert(amu_supported() != 0);
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assert(idx >= 0 && idx < AMU_GROUP1_NR_COUNTERS);
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return amu_group1_cnt_read_internal(idx);
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@ -82,7 +82,7 @@ uint64_t amu_group1_cnt_read(int idx)
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/* Write the group 1 counter identified by the given `idx` with `val`. */
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void amu_group1_cnt_write(int idx, uint64_t val)
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{
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assert(amu_supported());
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assert(amu_supported() != 0);
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assert(idx >= 0 && idx < AMU_GROUP1_NR_COUNTERS);
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amu_group1_cnt_write_internal(idx, val);
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@ -91,7 +91,7 @@ void amu_group1_cnt_write(int idx, uint64_t val)
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void amu_group1_set_evtype(int idx, unsigned int val)
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{
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assert(amu_supported());
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assert(amu_supported() != 0);
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assert(idx >= 0 && idx < AMU_GROUP1_NR_COUNTERS);
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amu_group1_set_evtype_internal(idx, val);
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@ -103,13 +103,14 @@ static void *amu_context_save(const void *arg)
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struct amu_ctx *ctx;
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int i;
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if (!amu_supported())
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if (amu_supported() == 0)
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return (void *)-1;
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ctx = &amu_ctxs[plat_my_core_pos()];
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/* Assert that group 0 counter configuration is what we expect */
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assert(read_amcntenset0() == AMU_GROUP0_COUNTERS_MASK);
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assert(read_amcntenset0() == AMU_GROUP0_COUNTERS_MASK &&
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read_amcntenset1() == AMU_GROUP1_COUNTERS_MASK);
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/*
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* Disable group 0 counters to avoid other observers like SCP sampling
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@ -131,17 +132,15 @@ static void *amu_context_save(const void *arg)
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static void *amu_context_restore(const void *arg)
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{
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struct amu_ctx *ctx;
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uint64_t features;
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int i;
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features = read_id_pfr0() >> ID_PFR0_AMU_SHIFT;
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if ((features & ID_PFR0_AMU_MASK) != 1)
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if (amu_supported() == 0)
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return (void *)-1;
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ctx = &amu_ctxs[plat_my_core_pos()];
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/* Counters were disabled in `amu_context_save()` */
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assert(read_amcntenset0() == 0);
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assert(read_amcntenset0() == 0 && read_amcntenset1() == 0);
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/* Restore group 0 counters */
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for (i = 0; i < AMU_GROUP0_NR_COUNTERS; i++)
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@ -18,7 +18,7 @@
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* uint64_t amu_group0_cnt_read_internal(int idx);
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*
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* Given `idx`, read the corresponding AMU counter
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* and return it in `r0`.
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* and return it in `r0` and `r1`.
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*/
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func amu_group0_cnt_read_internal
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#if ENABLE_ASSERTIONS
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@ -52,13 +52,15 @@ endfunc amu_group0_cnt_read_internal
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* void amu_group0_cnt_write_internal(int idx, uint64_t val);
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*
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* Given `idx`, write `val` to the corresponding AMU counter.
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* `idx` is passed in `r0` and `val` is passed in `r2` and `r3`.
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* `r1` is used as a scratch register.
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*/
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func amu_group0_cnt_write_internal
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#if ENABLE_ASSERTIONS
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/* `idx` should be between [0, 3] */
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mov r2, r0
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lsr r2, r2, #2
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cmp r2, #0
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mov r1, r0
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lsr r1, r1, #2
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cmp r1, #0
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ASM_ASSERT(eq)
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#endif
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@ -66,19 +68,19 @@ func amu_group0_cnt_write_internal
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* Given `idx` calculate address of stcopr16/bx lr instruction pair
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* in the table below.
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*/
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adr r2, 1f
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adr r1, 1f
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lsl r0, r0, #3 /* each stcopr16/bx lr sequence is 8 bytes */
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add r2, r2, r0
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bx r2
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add r1, r1, r0
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bx r1
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1:
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stcopr16 r0,r1, AMEVCNTR00 /* index 0 */
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stcopr16 r2, r3, AMEVCNTR00 /* index 0 */
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bx lr
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stcopr16 r0,r1, AMEVCNTR01 /* index 1 */
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stcopr16 r2, r3, AMEVCNTR01 /* index 1 */
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bx lr
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stcopr16 r0,r1, AMEVCNTR02 /* index 2 */
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stcopr16 r2, r3, AMEVCNTR02 /* index 2 */
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bx lr
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stcopr16 r0,r1, AMEVCNTR03 /* index 3 */
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stcopr16 r2, r3, AMEVCNTR03 /* index 3 */
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bx lr
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endfunc amu_group0_cnt_write_internal
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@ -86,14 +88,14 @@ endfunc amu_group0_cnt_write_internal
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* uint64_t amu_group1_cnt_read_internal(int idx);
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*
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* Given `idx`, read the corresponding AMU counter
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* and return it in `r0`.
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* and return it in `r0` and `r1`.
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*/
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func amu_group1_cnt_read_internal
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#if ENABLE_ASSERTIONS
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/* `idx` should be between [0, 15] */
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mov r2, r0
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lsr r2, r2, #4
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cmp r2, #0
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mov r1, r0
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lsr r1, r1, #4
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cmp r1, #0
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ASM_ASSERT(eq)
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#endif
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@ -107,37 +109,37 @@ func amu_group1_cnt_read_internal
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bx r1
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1:
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ldcopr16 r0,r1, AMEVCNTR10 /* index 0 */
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ldcopr16 r0, r1, AMEVCNTR10 /* index 0 */
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bx lr
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ldcopr16 r0,r1, AMEVCNTR11 /* index 1 */
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ldcopr16 r0, r1, AMEVCNTR11 /* index 1 */
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bx lr
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ldcopr16 r0,r1, AMEVCNTR12 /* index 2 */
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ldcopr16 r0, r1, AMEVCNTR12 /* index 2 */
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bx lr
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ldcopr16 r0,r1, AMEVCNTR13 /* index 3 */
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ldcopr16 r0, r1, AMEVCNTR13 /* index 3 */
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bx lr
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ldcopr16 r0,r1, AMEVCNTR14 /* index 4 */
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ldcopr16 r0, r1, AMEVCNTR14 /* index 4 */
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bx lr
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ldcopr16 r0,r1, AMEVCNTR15 /* index 5 */
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ldcopr16 r0, r1, AMEVCNTR15 /* index 5 */
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bx lr
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ldcopr16 r0,r1, AMEVCNTR16 /* index 6 */
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ldcopr16 r0, r1, AMEVCNTR16 /* index 6 */
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bx lr
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ldcopr16 r0,r1, AMEVCNTR17 /* index 7 */
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ldcopr16 r0, r1, AMEVCNTR17 /* index 7 */
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bx lr
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ldcopr16 r0,r1, AMEVCNTR18 /* index 8 */
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ldcopr16 r0, r1, AMEVCNTR18 /* index 8 */
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bx lr
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ldcopr16 r0,r1, AMEVCNTR19 /* index 9 */
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ldcopr16 r0, r1, AMEVCNTR19 /* index 9 */
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bx lr
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ldcopr16 r0,r1, AMEVCNTR1A /* index 10 */
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ldcopr16 r0, r1, AMEVCNTR1A /* index 10 */
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bx lr
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ldcopr16 r0,r1, AMEVCNTR1B /* index 11 */
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ldcopr16 r0, r1, AMEVCNTR1B /* index 11 */
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bx lr
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ldcopr16 r0,r1, AMEVCNTR1C /* index 12 */
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ldcopr16 r0, r1, AMEVCNTR1C /* index 12 */
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bx lr
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ldcopr16 r0,r1, AMEVCNTR1D /* index 13 */
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ldcopr16 r0, r1, AMEVCNTR1D /* index 13 */
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bx lr
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ldcopr16 r0,r1, AMEVCNTR1E /* index 14 */
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ldcopr16 r0, r1, AMEVCNTR1E /* index 14 */
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bx lr
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ldcopr16 r0,r1, AMEVCNTR1F /* index 15 */
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ldcopr16 r0, r1, AMEVCNTR1F /* index 15 */
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bx lr
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endfunc amu_group1_cnt_read_internal
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@ -145,13 +147,15 @@ endfunc amu_group1_cnt_read_internal
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* void amu_group1_cnt_write_internal(int idx, uint64_t val);
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*
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* Given `idx`, write `val` to the corresponding AMU counter.
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* `idx` is passed in `r0` and `val` is passed in `r2` and `r3`.
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* `r1` is used as a scratch register.
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*/
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func amu_group1_cnt_write_internal
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#if ENABLE_ASSERTIONS
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/* `idx` should be between [0, 15] */
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mov r2, r0
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lsr r2, r2, #4
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cmp r2, #0
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mov r1, r0
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lsr r1, r1, #4
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cmp r1, #0
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ASM_ASSERT(eq)
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#endif
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@ -159,43 +163,43 @@ func amu_group1_cnt_write_internal
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* Given `idx` calculate address of ldcopr16/bx lr instruction pair
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* in the table below.
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*/
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adr r2, 1f
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adr r1, 1f
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lsl r0, r0, #3 /* each stcopr16/bx lr sequence is 8 bytes */
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add r2, r2, r0
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bx r2
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add r1, r1, r0
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bx r1
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1:
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stcopr16 r0,r1, AMEVCNTR10 /* index 0 */
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stcopr16 r2, r3, AMEVCNTR10 /* index 0 */
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bx lr
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stcopr16 r0,r1, AMEVCNTR11 /* index 1 */
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stcopr16 r2, r3, AMEVCNTR11 /* index 1 */
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bx lr
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stcopr16 r0,r1, AMEVCNTR12 /* index 2 */
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stcopr16 r2, r3, AMEVCNTR12 /* index 2 */
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bx lr
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stcopr16 r0,r1, AMEVCNTR13 /* index 3 */
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stcopr16 r2, r3, AMEVCNTR13 /* index 3 */
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bx lr
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stcopr16 r0,r1, AMEVCNTR14 /* index 4 */
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stcopr16 r2, r3, AMEVCNTR14 /* index 4 */
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bx lr
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stcopr16 r0,r1, AMEVCNTR15 /* index 5 */
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stcopr16 r2, r3, AMEVCNTR15 /* index 5 */
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bx lr
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stcopr16 r0,r1, AMEVCNTR16 /* index 6 */
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stcopr16 r2, r3, AMEVCNTR16 /* index 6 */
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bx lr
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stcopr16 r0,r1, AMEVCNTR17 /* index 7 */
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stcopr16 r2, r3, AMEVCNTR17 /* index 7 */
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bx lr
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stcopr16 r0,r1, AMEVCNTR18 /* index 8 */
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stcopr16 r2, r3, AMEVCNTR18 /* index 8 */
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bx lr
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stcopr16 r0,r1, AMEVCNTR19 /* index 9 */
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stcopr16 r2, r3, AMEVCNTR19 /* index 9 */
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bx lr
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stcopr16 r0,r1, AMEVCNTR1A /* index 10 */
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stcopr16 r2, r3, AMEVCNTR1A /* index 10 */
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bx lr
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stcopr16 r0,r1, AMEVCNTR1B /* index 11 */
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stcopr16 r2, r3, AMEVCNTR1B /* index 11 */
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bx lr
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stcopr16 r0,r1, AMEVCNTR1C /* index 12 */
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stcopr16 r2, r3, AMEVCNTR1C /* index 12 */
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bx lr
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stcopr16 r0,r1, AMEVCNTR1D /* index 13 */
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stcopr16 r2, r3, AMEVCNTR1D /* index 13 */
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bx lr
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stcopr16 r0,r1, AMEVCNTR1E /* index 14 */
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stcopr16 r2, r3, AMEVCNTR1E /* index 14 */
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bx lr
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stcopr16 r0,r1, AMEVCNTR1F /* index 15 */
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stcopr16 r2, r3, AMEVCNTR1F /* index 15 */
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bx lr
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endfunc amu_group1_cnt_write_internal
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@ -230,36 +234,36 @@ func amu_group1_set_evtype_internal
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bx r2
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1:
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stcopr r0, AMEVTYPER10 /* index 0 */
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stcopr r1, AMEVTYPER10 /* index 0 */
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bx lr
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stcopr r0, AMEVTYPER11 /* index 1 */
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stcopr r1, AMEVTYPER11 /* index 1 */
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bx lr
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stcopr r0, AMEVTYPER12 /* index 2 */
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stcopr r1, AMEVTYPER12 /* index 2 */
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bx lr
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stcopr r0, AMEVTYPER13 /* index 3 */
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stcopr r1, AMEVTYPER13 /* index 3 */
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bx lr
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stcopr r0, AMEVTYPER14 /* index 4 */
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stcopr r1, AMEVTYPER14 /* index 4 */
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bx lr
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stcopr r0, AMEVTYPER15 /* index 5 */
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stcopr r1, AMEVTYPER15 /* index 5 */
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bx lr
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stcopr r0, AMEVTYPER16 /* index 6 */
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stcopr r1, AMEVTYPER16 /* index 6 */
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bx lr
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stcopr r0, AMEVTYPER17 /* index 7 */
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stcopr r1, AMEVTYPER17 /* index 7 */
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bx lr
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stcopr r0, AMEVTYPER18 /* index 8 */
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stcopr r1, AMEVTYPER18 /* index 8 */
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bx lr
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stcopr r0, AMEVTYPER19 /* index 9 */
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stcopr r1, AMEVTYPER19 /* index 9 */
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bx lr
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stcopr r0, AMEVTYPER1A /* index 10 */
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stcopr r1, AMEVTYPER1A /* index 10 */
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bx lr
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stcopr r0, AMEVTYPER1B /* index 11 */
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stcopr r1, AMEVTYPER1B /* index 11 */
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bx lr
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stcopr r0, AMEVTYPER1C /* index 12 */
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stcopr r1, AMEVTYPER1C /* index 12 */
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bx lr
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stcopr r0, AMEVTYPER1D /* index 13 */
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stcopr r1, AMEVTYPER1D /* index 13 */
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bx lr
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stcopr r0, AMEVTYPER1E /* index 14 */
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stcopr r1, AMEVTYPER1E /* index 14 */
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bx lr
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stcopr r0, AMEVTYPER1F /* index 15 */
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stcopr r1, AMEVTYPER1F /* index 15 */
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bx lr
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endfunc amu_group1_set_evtype_internal
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@ -37,7 +37,7 @@ void amu_enable(int el2_unused)
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{
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uint64_t v;
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if (!amu_supported())
|
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if (amu_supported() == 0)
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return;
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if (el2_unused) {
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|
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@ -67,7 +67,7 @@ void amu_enable(int el2_unused)
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/* Read the group 0 counter identified by the given `idx`. */
|
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uint64_t amu_group0_cnt_read(int idx)
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{
|
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assert(amu_supported());
|
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assert(amu_supported() != 0);
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assert(idx >= 0 && idx < AMU_GROUP0_NR_COUNTERS);
|
||||
|
||||
return amu_group0_cnt_read_internal(idx);
|
||||
|
|
@ -76,7 +76,7 @@ uint64_t amu_group0_cnt_read(int idx)
|
|||
/* Write the group 0 counter identified by the given `idx` with `val`. */
|
||||
void amu_group0_cnt_write(int idx, uint64_t val)
|
||||
{
|
||||
assert(amu_supported());
|
||||
assert(amu_supported() != 0);
|
||||
assert(idx >= 0 && idx < AMU_GROUP0_NR_COUNTERS);
|
||||
|
||||
amu_group0_cnt_write_internal(idx, val);
|
||||
|
|
@ -86,7 +86,7 @@ void amu_group0_cnt_write(int idx, uint64_t val)
|
|||
/* Read the group 1 counter identified by the given `idx`. */
|
||||
uint64_t amu_group1_cnt_read(int idx)
|
||||
{
|
||||
assert(amu_supported());
|
||||
assert(amu_supported() != 0);
|
||||
assert(idx >= 0 && idx < AMU_GROUP1_NR_COUNTERS);
|
||||
|
||||
return amu_group1_cnt_read_internal(idx);
|
||||
|
|
@ -95,7 +95,7 @@ uint64_t amu_group1_cnt_read(int idx)
|
|||
/* Write the group 1 counter identified by the given `idx` with `val`. */
|
||||
void amu_group1_cnt_write(int idx, uint64_t val)
|
||||
{
|
||||
assert(amu_supported());
|
||||
assert(amu_supported() != 0);
|
||||
assert(idx >= 0 && idx < AMU_GROUP1_NR_COUNTERS);
|
||||
|
||||
amu_group1_cnt_write_internal(idx, val);
|
||||
|
|
@ -108,7 +108,7 @@ void amu_group1_cnt_write(int idx, uint64_t val)
|
|||
*/
|
||||
void amu_group1_set_evtype(int idx, unsigned int val)
|
||||
{
|
||||
assert(amu_supported());
|
||||
assert(amu_supported() != 0);
|
||||
assert (idx >= 0 && idx < AMU_GROUP1_NR_COUNTERS);
|
||||
|
||||
amu_group1_set_evtype_internal(idx, val);
|
||||
|
|
@ -120,7 +120,7 @@ static void *amu_context_save(const void *arg)
|
|||
struct amu_ctx *ctx = &amu_ctxs[plat_my_core_pos()];
|
||||
int i;
|
||||
|
||||
if (!amu_supported())
|
||||
if (amu_supported() == 0)
|
||||
return (void *)-1;
|
||||
|
||||
/* Assert that group 0/1 counter configuration is what we expect */
|
||||
|
|
@ -154,7 +154,7 @@ static void *amu_context_restore(const void *arg)
|
|||
struct amu_ctx *ctx = &amu_ctxs[plat_my_core_pos()];
|
||||
int i;
|
||||
|
||||
if (!amu_supported())
|
||||
if (amu_supported() == 0)
|
||||
return (void *)-1;
|
||||
|
||||
/* Counters were disabled in `amu_context_save()` */
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
|
@ -14,14 +14,21 @@
|
|||
*/
|
||||
#define psb_csync() asm volatile("hint #17")
|
||||
|
||||
void spe_enable(int el2_unused)
|
||||
int spe_supported(void)
|
||||
{
|
||||
uint64_t features;
|
||||
|
||||
features = read_id_aa64dfr0_el1() >> ID_AA64DFR0_PMS_SHIFT;
|
||||
if ((features & ID_AA64DFR0_PMS_MASK) == 1) {
|
||||
return (features & ID_AA64DFR0_PMS_MASK) == 1;
|
||||
}
|
||||
|
||||
void spe_enable(int el2_unused)
|
||||
{
|
||||
uint64_t v;
|
||||
|
||||
if (spe_supported() == 0)
|
||||
return;
|
||||
|
||||
if (el2_unused) {
|
||||
/*
|
||||
* MDCR_EL2.TPMS (ARM v8.2): Do not trap statistical
|
||||
|
|
@ -45,17 +52,15 @@ void spe_enable(int el2_unused)
|
|||
v = read_mdcr_el3();
|
||||
v |= MDCR_NSPB(MDCR_NSPB_EL1);
|
||||
write_mdcr_el3(v);
|
||||
}
|
||||
}
|
||||
|
||||
void spe_disable(void)
|
||||
{
|
||||
uint64_t features;
|
||||
|
||||
features = read_id_aa64dfr0_el1() >> ID_AA64DFR0_PMS_SHIFT;
|
||||
if ((features & ID_AA64DFR0_PMS_MASK) == 1) {
|
||||
uint64_t v;
|
||||
|
||||
if (spe_supported() == 0)
|
||||
return;
|
||||
|
||||
/* Drain buffered data */
|
||||
psb_csync();
|
||||
dsbnsh();
|
||||
|
|
@ -65,20 +70,16 @@ void spe_disable(void)
|
|||
v &= ~(1ULL << 0);
|
||||
write_pmblimitr_el1(v);
|
||||
isb();
|
||||
}
|
||||
}
|
||||
|
||||
static void *spe_drain_buffers_hook(const void *arg)
|
||||
{
|
||||
uint64_t features;
|
||||
if (spe_supported() == 0)
|
||||
return (void *)-1;
|
||||
|
||||
features = read_id_aa64dfr0_el1() >> ID_AA64DFR0_PMS_SHIFT;
|
||||
if ((features & ID_AA64DFR0_PMS_MASK) == 1) {
|
||||
/* Drain buffered data */
|
||||
psb_csync();
|
||||
dsbnsh();
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
|
@ -9,14 +9,21 @@
|
|||
#include <pubsub.h>
|
||||
#include <sve.h>
|
||||
|
||||
static void *disable_sve_hook(const void *arg)
|
||||
int sve_supported(void)
|
||||
{
|
||||
uint64_t features;
|
||||
|
||||
features = read_id_aa64pfr0_el1() >> ID_AA64PFR0_SVE_SHIFT;
|
||||
if ((features & ID_AA64PFR0_SVE_MASK) == 1) {
|
||||
return (features & ID_AA64PFR0_SVE_MASK) == 1;
|
||||
}
|
||||
|
||||
static void *disable_sve_hook(const void *arg)
|
||||
{
|
||||
uint64_t cptr;
|
||||
|
||||
if (sve_supported() == 0)
|
||||
return (void *)-1;
|
||||
|
||||
/*
|
||||
* Disable SVE, SIMD and FP access for the Secure world.
|
||||
* As the SIMD/FP registers are part of the SVE Z-registers, any
|
||||
|
|
@ -32,18 +39,16 @@ static void *disable_sve_hook(const void *arg)
|
|||
* No explicit ISB required here as ERET to switch to Secure
|
||||
* world covers it
|
||||
*/
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void *enable_sve_hook(const void *arg)
|
||||
{
|
||||
uint64_t features;
|
||||
|
||||
features = read_id_aa64pfr0_el1() >> ID_AA64PFR0_SVE_SHIFT;
|
||||
if ((features & ID_AA64PFR0_SVE_MASK) == 1) {
|
||||
uint64_t cptr;
|
||||
|
||||
if (sve_supported() == 0)
|
||||
return (void *)-1;
|
||||
|
||||
/*
|
||||
* Enable SVE, SIMD and FP access for the Non-secure world.
|
||||
*/
|
||||
|
|
@ -55,17 +60,16 @@ static void *enable_sve_hook(const void *arg)
|
|||
* No explicit ISB required here as ERET to switch to Non-secure
|
||||
* world covers it
|
||||
*/
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
void sve_enable(int el2_unused)
|
||||
{
|
||||
uint64_t features;
|
||||
|
||||
features = read_id_aa64pfr0_el1() >> ID_AA64PFR0_SVE_SHIFT;
|
||||
if ((features & ID_AA64PFR0_SVE_MASK) == 1) {
|
||||
uint64_t cptr;
|
||||
|
||||
if (sve_supported() == 0)
|
||||
return;
|
||||
|
||||
#if CTX_INCLUDE_FPREGS
|
||||
/*
|
||||
* CTX_INCLUDE_FPREGS is not supported on SVE enabled systems.
|
||||
|
|
@ -119,7 +123,6 @@ void sve_enable(int el2_unused)
|
|||
* No explicit ISB required here as ERET to switch to
|
||||
* Non-secure world covers it.
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
SUBSCRIBE_TO_EVENT(cm_exited_normal_world, disable_sve_hook);
|
||||
|
|
|
|||
Loading…
Reference in New Issue