Use secure timer to generate S-EL1 interrupts
This patch adds support in the TSP to program the secure physical generic timer to generate a EL-1 interrupt every half second. It also adds support for maintaining the timer state across power management operations. The TSPD ensures that S-EL1 can access the timer by programming the SCR_EL3.ST bit. This patch does not actually enable the timer. This will be done in a subsequent patch once the complete framework for handling S-EL1 interrupts is in place. Change-Id: I1b3985cfb50262f60824be3a51c6314ce90571bc
This commit is contained in:
Achin Gupta
parent
dce74b891e
commit
fa9c08b7d1
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@ -32,7 +32,8 @@ BL32_SOURCES += bl32/tsp/tsp_main.c \
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bl32/tsp/aarch64/tsp_entrypoint.S \
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bl32/tsp/aarch64/tsp_request.S \
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common/aarch64/early_exceptions.S \
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lib/locks/exclusive/spinlock.S
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lib/locks/exclusive/spinlock.S \
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bl32/tsp/tsp_timer.c
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BL32_LINKERFILE := bl32/tsp/tsp.ld.S
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@ -0,0 +1,106 @@
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/*
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* Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch_helpers.h>
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#include <assert.h>
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#include <tsp.h>
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/*******************************************************************************
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* Data structure to keep track of per-cpu secure generic timer context across
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* power management operations.
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******************************************************************************/
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typedef struct timer_context {
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uint64_t cval;
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uint32_t ctl;
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} timer_context_t;
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static timer_context_t pcpu_timer_context[PLATFORM_CORE_COUNT];
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/*******************************************************************************
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* This function initializes the generic timer to fire every 0.5 second
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******************************************************************************/
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void tsp_generic_timer_start()
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{
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uint64_t cval;
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uint32_t ctl = 0;
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/* The timer will fire every 0.5 second */
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cval = read_cntpct_el0() + (read_cntfrq_el0() >> 1);
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write_cntps_cval_el1(cval);
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/* Enable the secure physical timer */
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set_cntp_ctl_enable(ctl);
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write_cntps_ctl_el1(ctl);
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}
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/*******************************************************************************
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* This function deasserts the timer interrupt and sets it up again
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******************************************************************************/
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void tsp_generic_timer_handler()
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{
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/* Ensure that the timer did assert the interrupt */
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assert(get_cntp_ctl_istatus(read_cntps_ctl_el1()));
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/* Disable the timer and reprogram it */
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write_cntps_ctl_el1(0);
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tsp_generic_timer_start();
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}
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/*******************************************************************************
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* This function deasserts the timer interrupt prior to cpu power down
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******************************************************************************/
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void tsp_generic_timer_stop()
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{
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/* Disable the timer */
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write_cntps_ctl_el1(0);
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}
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/*******************************************************************************
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* This function saves the timer context prior to cpu suspension
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******************************************************************************/
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void tsp_generic_timer_save()
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{
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uint32_t linear_id = platform_get_core_pos(read_mpidr());
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pcpu_timer_context[linear_id].cval = read_cntps_cval_el1();
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pcpu_timer_context[linear_id].ctl = read_cntps_ctl_el1();
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flush_dcache_range((uint64_t) &pcpu_timer_context[linear_id],
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sizeof(pcpu_timer_context[linear_id]));
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}
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/*******************************************************************************
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* This function restores the timer context post cpu resummption
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******************************************************************************/
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void tsp_generic_timer_restore()
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{
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uint32_t linear_id = platform_get_core_pos(read_mpidr());
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write_cntps_cval_el1(pcpu_timer_context[linear_id].cval);
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write_cntps_ctl_el1(pcpu_timer_context[linear_id].ctl);
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}
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@ -196,6 +196,13 @@ extern tsp_args_t *tsp_cpu_off_main(uint64_t arg0,
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uint64_t arg5,
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uint64_t arg6,
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uint64_t arg7);
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/* Generic Timer functions */
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extern void tsp_generic_timer_start(void);
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extern void tsp_generic_timer_handler(void);
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extern void tsp_generic_timer_stop(void);
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extern void tsp_generic_timer_save(void);
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extern void tsp_generic_timer_restore(void);
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#endif /* __ASSEMBLY__ */
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#endif /* __BL2_H__ */
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@ -265,6 +265,28 @@
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((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)
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/* Physical timer control register bit fields shifts and masks */
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#define CNTP_CTL_ENABLE_SHIFT 0
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#define CNTP_CTL_IMASK_SHIFT 1
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#define CNTP_CTL_ISTATUS_SHIFT 2
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#define CNTP_CTL_ENABLE_MASK 1
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#define CNTP_CTL_IMASK_MASK 1
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#define CNTP_CTL_ISTATUS_MASK 1
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#define get_cntp_ctl_enable(x) ((x >> CNTP_CTL_ENABLE_SHIFT) & \
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CNTP_CTL_ENABLE_MASK)
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#define get_cntp_ctl_imask(x) ((x >> CNTP_CTL_IMASK_SHIFT) & \
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CNTP_CTL_IMASK_MASK)
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#define get_cntp_ctl_istatus(x) ((x >> CNTP_CTL_ISTATUS_SHIFT) & \
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CNTP_CTL_ISTATUS_MASK)
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#define set_cntp_ctl_enable(x) (x |= 1 << CNTP_CTL_ENABLE_SHIFT)
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#define set_cntp_ctl_imask(x) (x |= 1 << CNTP_CTL_IMASK_SHIFT)
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#define clr_cntp_ctl_enable(x) (x &= ~(1 << CNTP_CTL_ENABLE_SHIFT))
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#define clr_cntp_ctl_imask(x) (x &= ~(1 << CNTP_CTL_IMASK_SHIFT))
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/* Miscellaneous MMU related constants */
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#define NUM_2MB_IN_GB (1 << 9)
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#define NUM_4K_IN_2MB (1 << 9)
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@ -202,6 +202,10 @@ extern unsigned long read_cptr_el3(void);
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extern unsigned long read_cpacr(void);
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extern unsigned long read_cpuectlr(void);
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extern unsigned int read_cntfrq_el0(void);
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extern unsigned int read_cntps_ctl_el1(void);
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extern unsigned int read_cntps_tval_el1(void);
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extern unsigned long read_cntps_cval_el1(void);
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extern unsigned long read_cntpct_el0(void);
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extern unsigned long read_cnthctl_el2(void);
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extern unsigned long read_tpidr_el3(void);
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@ -210,6 +214,9 @@ extern void write_scr(unsigned long);
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extern void write_hcr(unsigned long);
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extern void write_cpacr(unsigned long);
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extern void write_cntfrq_el0(unsigned int);
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extern void write_cntps_ctl_el1(unsigned int);
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extern void write_cntps_tval_el1(unsigned int);
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extern void write_cntps_cval_el1(unsigned long);
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extern void write_cnthctl_el2(unsigned long);
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extern void write_vbar_el1(unsigned long);
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@ -142,6 +142,15 @@
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.globl read_cntfrq_el0
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.globl write_cntfrq_el0
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.globl read_cntps_ctl_el1
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.globl write_cntps_ctl_el1
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.globl read_cntps_cval_el1
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.globl write_cntps_cval_el1
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.globl read_cntps_tval_el1
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.globl write_cntps_tval_el1
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.globl read_scr
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.globl write_scr
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@ -151,6 +160,7 @@
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.globl read_midr
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.globl read_mpidr
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.globl read_cntpct_el0
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.globl read_current_el
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.globl read_id_pfr1_el1
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.globl read_id_aa64pfr0_el1
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@ -672,6 +682,33 @@ func write_cntfrq_el0
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msr cntfrq_el0, x0
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ret
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func read_cntps_ctl_el1
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mrs x0, cntps_ctl_el1
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ret
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func write_cntps_ctl_el1
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msr cntps_ctl_el1, x0
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ret
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func read_cntps_cval_el1
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mrs x0, cntps_cval_el1
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ret
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func write_cntps_cval_el1
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msr cntps_cval_el1, x0
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ret
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func read_cntps_tval_el1
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mrs x0, cntps_tval_el1
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ret
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func write_cntps_tval_el1
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msr cntps_tval_el1, x0
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ret
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func read_cntpct_el0
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mrs x0, cntpct_el0
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ret
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func read_cpuectlr
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mrs x0, CPUECTLR_EL1
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@ -65,10 +65,14 @@ int32_t tspd_init_secure_context(uint64_t entrypoint,
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*/
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memset(tsp_ctx, 0, sizeof(*tsp_ctx));
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/* Set the right security state and register width for the SP */
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/*
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* Set the right security state, register width and enable access to
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* the secure physical timer for the SP.
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*/
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scr = read_scr();
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scr &= ~SCR_NS_BIT;
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scr &= ~SCR_RW_BIT;
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scr |= SCR_ST_BIT;
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if (rw == TSP_AARCH64)
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scr |= SCR_RW_BIT;
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