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Avoid the use of linker *_SIZE__ macros 

The use of end addresses is preferred over the size of sections.
This was done for some AARCH64 files for PIE with commit [1],
and some extra explanations can be found in its commit message.
Align the missing AARCH64 files.

For AARCH32 files, this is required to prepare PIE support introduction.

 [1] f1722b693d ("PIE: Use PC relative adrp/adr for symbol reference")

Change-Id: I8f1c06580182b10c680310850f72904e58a54d7d
Signed-off-by: Yann Gautier <yann.gautier@st.com>
This commit is contained in:
Yann Gautier 2020-08-18 14:42:41 +02:00 committed by Yann Gautier
parent 617632bf83
commit fb4f511f9b
5 changed files with 32 additions and 17 deletions
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8
bl2/aarch32/bl2_entrypoint.S
View File

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -80,12 +80,14 @@ func bl2_entrypoint
* --------------------------------------------- * ---------------------------------------------
*/ */
ldr r0, =__BSS_START__ ldr r0, =__BSS_START__
ldr r1, =__BSS_SIZE__ ldr r1, =__BSS_END__
sub r1, r1, r0
bl zeromem bl zeromem
#if USE_COHERENT_MEM #if USE_COHERENT_MEM
ldr r0, =__COHERENT_RAM_START__ ldr r0, =__COHERENT_RAM_START__
ldr r1, =__COHERENT_RAM_UNALIGNED_SIZE__ ldr r1, =__COHERENT_RAM_END_UNALIGNED__
sub r1, r1, r0
bl zeromem bl zeromem
#endif #endif

5
bl2u/aarch32/bl2u_entrypoint.S
View File

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -79,7 +79,8 @@ func bl2u_entrypoint
* --------------------------------------------- * ---------------------------------------------
*/ */
ldr r0, =__BSS_START__ ldr r0, =__BSS_START__
ldr r1, =__BSS_SIZE__ ldr r1, =__BSS_END__
sub r1, r1, r0
bl zeromem bl zeromem
/* -------------------------------------------- /* --------------------------------------------

9
bl2u/aarch64/bl2u_entrypoint.S
View File

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -69,8 +69,11 @@ func bl2u_entrypoint
* - the coherent memory section. * - the coherent memory section.
* --------------------------------------------- * ---------------------------------------------
*/ */
ldr x0, =__BSS_START__ adrp x0, __BSS_START__
ldr x1, =__BSS_SIZE__ add x0, x0, :lo12:__BSS_START__
adrp x1, __BSS_END__
add x1, x1, :lo12:__BSS_END__
sub x1, x1, x0
bl zeromem bl zeromem
/* -------------------------------------------- /* --------------------------------------------

16
bl32/tsp/aarch64/tsp_entrypoint.S
View File

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -114,13 +114,19 @@ func tsp_entrypoint _align=3
* - the coherent memory section. * - the coherent memory section.
* --------------------------------------------- * ---------------------------------------------
*/ */
ldr x0, =__BSS_START__ adrp x0, __BSS_START__
ldr x1, =__BSS_SIZE__ add x0, x0, :lo12:__BSS_START__
adrp x1, __BSS_END__
add x1, x1, :lo12:__BSS_END__
sub x1, x1, x0
bl zeromem bl zeromem
#if USE_COHERENT_MEM #if USE_COHERENT_MEM
ldr x0, =__COHERENT_RAM_START__ adrp x0, __COHERENT_RAM_START__
ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__ add x0, x0, :lo12:__COHERENT_RAM_START__
adrp x1, __COHERENT_RAM_END_UNALIGNED__
add x1, x1, :lo12:__COHERENT_RAM_END_UNALIGNED__
sub x1, x1, x0
bl zeromem bl zeromem
#endif #endif

11
include/arch/aarch32/el3_common_macros.S
View File

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -339,12 +339,14 @@
*/ */
mov r7, r12 mov r7, r12
ldr r0, =__BSS_START__ ldr r0, =__BSS_START__
ldr r1, =__BSS_SIZE__ ldr r1, =__BSS_END__
sub r1, r1, r0
bl zeromem bl zeromem
#if USE_COHERENT_MEM #if USE_COHERENT_MEM
ldr r0, =__COHERENT_RAM_START__ ldr r0, =__COHERENT_RAM_START__
ldr r1, =__COHERENT_RAM_UNALIGNED_SIZE__ ldr r1, =__COHERENT_RAM_END_UNALIGNED__
sub r1, r1, r0
bl zeromem bl zeromem
#endif #endif
@ -358,7 +360,8 @@
*/ */
ldr r0, =__DATA_RAM_START__ ldr r0, =__DATA_RAM_START__
ldr r1, =__DATA_ROM_START__ ldr r1, =__DATA_ROM_START__
ldr r2, =__DATA_SIZE__ ldr r2, =__DATA_RAM_END__
sub r2, r2, r0
bl memcpy4 bl memcpy4
#endif #endif
.endif /* _init_c_runtime */ .endif /* _init_c_runtime */