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Tegra: fix MISRA defects in tegra_bl31_setup.c 

Main fixes:

Add parentheses to avoid implicit operator precedence [Rule 12.1]

Fixed if statement conditional to be essentially boolean [Rule 14.4]

Added curly braces ({}) around if statements in order to
make them compound [Rule 15.6]

Voided non c-library functions whose return types are not used [Rule 17.7]

Bug 200272157

Change-Id: Ic3ab5a3de95aeb6d2265df940f7fb35ea0f19ab0
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
This commit is contained in:
Varun Wadekar 2019-01-02 10:48:18 -08:00
parent 647d4a035a
commit fcf23a1419
2 changed files with 53 additions and 53 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

100
plat/nvidia/tegra/common/tegra_bl31_setup.c
View File

@ -40,20 +40,19 @@ extern void memcpy16(void *dest, const void *src, unsigned int length);
* of trusted SRAM
******************************************************************************/
IMPORT_SYM(unsigned long, __RW_START__, BL31_RW_START);
IMPORT_SYM(unsigned long, __RW_END__, BL31_RW_END);
IMPORT_SYM(unsigned long, __RODATA_START__, BL31_RODATA_BASE);
IMPORT_SYM(unsigned long, __RODATA_END__, BL31_RODATA_END);
IMPORT_SYM(unsigned long, __TEXT_START__, TEXT_START);
IMPORT_SYM(unsigned long, __TEXT_END__, TEXT_END);
IMPORT_SYM(uint64_t, __RW_START__, BL31_RW_START);
IMPORT_SYM(uint64_t, __RW_END__, BL31_RW_END);
IMPORT_SYM(uint64_t, __RODATA_START__, BL31_RODATA_BASE);
IMPORT_SYM(uint64_t, __RODATA_END__, BL31_RODATA_END);
IMPORT_SYM(uint64_t, __TEXT_START__, TEXT_START);
IMPORT_SYM(uint64_t, __TEXT_END__, TEXT_END);
extern uint64_t tegra_bl31_phys_base;
extern uint64_t tegra_console_base;
static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info;
static plat_params_from_bl2_t plat_bl31_params_from_bl2 = {
.tzdram_size = (uint64_t)TZDRAM_SIZE
.tzdram_size = TZDRAM_SIZE
};
static unsigned long bl32_mem_size;
static unsigned long bl32_boot_params;
@ -93,14 +92,16 @@ plat_params_from_bl2_t *plat_get_bl31_plat_params(void)
******************************************************************************/
entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
{
if (type == NON_SECURE)
return &bl33_image_ep_info;
entry_point_info_t *ep = NULL;
/* return BL32 entry point info if it is valid */
if (type == SECURE && bl32_image_ep_info.pc)
return &bl32_image_ep_info;
if (type == NON_SECURE) {
ep = &bl33_image_ep_info;
} else if ((type == SECURE) && (bl32_image_ep_info.pc != 0U)) {
ep = &bl32_image_ep_info;
}
return NULL;
return ep;
}
/*******************************************************************************
@ -131,10 +132,12 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
* might use custom ways to get arguments, so provide handlers which
* they can override.
*/
if (arg_from_bl2 == NULL)
if (arg_from_bl2 == NULL) {
arg_from_bl2 = plat_get_bl31_params();
if (plat_params == NULL)
}
if (plat_params == NULL) {
plat_params = plat_get_bl31_plat_params();
}
/*
* Copy BL3-3, BL3-2 entry point information.
@ -144,7 +147,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
assert(arg_from_bl2->bl33_ep_info);
bl33_image_ep_info = *arg_from_bl2->bl33_ep_info;
if (arg_from_bl2->bl32_ep_info) {
if (arg_from_bl2->bl32_ep_info != NULL) {
bl32_image_ep_info = *arg_from_bl2->bl32_ep_info;
bl32_mem_size = arg_from_bl2->bl32_ep_info->args.arg0;
bl32_boot_params = arg_from_bl2->bl32_ep_info->args.arg2;
@ -163,14 +166,15 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
* It is very important that we run either from TZDRAM or TZSRAM base.
* Add an explicit check here.
*/
if ((plat_bl31_params_from_bl2.tzdram_base != BL31_BASE) &&
(TEGRA_TZRAM_BASE != BL31_BASE))
if ((plat_bl31_params_from_bl2.tzdram_base != (uint64_t)BL31_BASE) &&
(TEGRA_TZRAM_BASE != BL31_BASE)) {
panic();
}
/*
* Reference clock used by the FPGAs is a lot slower.
*/
if (tegra_platform_is_fpga() == 1U) {
if (tegra_platform_is_fpga()) {
console_clock = TEGRA_BOOT_UART_CLK_13_MHZ;
} else {
console_clock = TEGRA_BOOT_UART_CLK_408_MHZ;
@ -182,11 +186,11 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
*/
tegra_console_base = plat_get_console_from_id(plat_params->uart_id);
if (tegra_console_base != (uint64_t)0) {
if (tegra_console_base != 0U) {
/*
* Configure the UART port to be used as the console
*/
console_init(tegra_console_base, console_clock,
(void)console_init(tegra_console_base, console_clock,
TEGRA_CONSOLE_BAUDRATE);
}
@ -199,14 +203,14 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
* Do initial security configuration to allow DRAM/device access.
*/
tegra_memctrl_tzdram_setup(plat_bl31_params_from_bl2.tzdram_base,
plat_bl31_params_from_bl2.tzdram_size);
(uint32_t)plat_bl31_params_from_bl2.tzdram_size);
/*
* The previous bootloader might not have placed the BL32 image
* inside the TZDRAM. We check the BL32 image info to find out
* the base/PC values and relocate the image if necessary.
*/
if (arg_from_bl2->bl32_image_info) {
if (arg_from_bl2->bl32_image_info != NULL) {
bl32_img_info = *arg_from_bl2->bl32_image_info;
@ -223,11 +227,11 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
assert(bl32_image_ep_info.pc < tzdram_end);
/* relocate BL32 */
if (bl32_start >= tzdram_end || bl32_end <= tzdram_start) {
if ((bl32_start >= tzdram_end) || (bl32_end <= tzdram_start)) {
INFO("Relocate BL32 to TZDRAM\n");
memcpy16((void *)(uintptr_t)bl32_image_ep_info.pc,
(void)memcpy16((void *)(uintptr_t)bl32_image_ep_info.pc,
(void *)(uintptr_t)bl32_start,
bl32_img_info.image_size);
@ -264,8 +268,6 @@ void plat_trusty_set_boot_args(aapcs64_params_t *args)
******************************************************************************/
void bl31_platform_setup(void)
{
uint32_t tmp_reg;
/* Initialize the gic cpu and distributor interfaces */
plat_gic_setup();
@ -285,10 +287,6 @@ void bl31_platform_setup(void)
*/
tegra_memctrl_tzram_setup(TEGRA_TZRAM_BASE, TEGRA_TZRAM_SIZE);
/* Set the next EL to be AArch64 */
tmp_reg = SCR_RES1_BITS | SCR_RW_BIT;
write_scr(tmp_reg);
INFO("BL3-1: Tegra platform setup complete\n");
}
@ -315,17 +313,17 @@ void bl31_plat_runtime_setup(void)
******************************************************************************/
void bl31_plat_arch_setup(void)
{
unsigned long rw_start = BL31_RW_START;
unsigned long rw_size = BL31_RW_END - BL31_RW_START;
unsigned long rodata_start = BL31_RODATA_BASE;
unsigned long rodata_size = BL31_RODATA_END - BL31_RODATA_BASE;
unsigned long code_base = TEXT_START;
unsigned long code_size = TEXT_END - TEXT_START;
uint64_t rw_start = BL31_RW_START;
uint64_t rw_size = BL31_RW_END - BL31_RW_START;
uint64_t rodata_start = BL31_RODATA_BASE;
uint64_t rodata_size = BL31_RODATA_END - BL31_RODATA_BASE;
uint64_t code_base = TEXT_START;
uint64_t code_size = TEXT_END - TEXT_START;
const mmap_region_t *plat_mmio_map = NULL;
#if USE_COHERENT_MEM
unsigned long coh_start, coh_size;
uint32_t coh_start, coh_size;
#endif
plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
/* add memory regions */
mmap_add_region(rw_start, rw_start,
@ -352,21 +350,22 @@ void bl31_plat_arch_setup(void)
mmap_add_region(coh_start, coh_start,
coh_size,
MT_DEVICE | MT_RW | MT_SECURE);
(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE);
#endif
/* map on-chip free running uS timer */
mmap_add_region(page_align((uint64_t)TEGRA_TMRUS_BASE, 0),
page_align((uint64_t)TEGRA_TMRUS_BASE, 0),
(uint64_t)TEGRA_TMRUS_SIZE,
MT_DEVICE | MT_RO | MT_SECURE);
mmap_add_region(page_align(TEGRA_TMRUS_BASE, 0),
page_align(TEGRA_TMRUS_BASE, 0),
TEGRA_TMRUS_SIZE,
(uint8_t)MT_DEVICE | (uint8_t)MT_RO | (uint8_t)MT_SECURE);
/* add MMIO space */
plat_mmio_map = plat_get_mmio_map();
if (plat_mmio_map)
if (plat_mmio_map != NULL) {
mmap_add(plat_mmio_map);
else
} else {
WARN("MMIO map not available\n");
}
/* set up translation tables */
init_xlat_tables();
@ -380,16 +379,17 @@ void bl31_plat_arch_setup(void)
/*******************************************************************************
* Check if the given NS DRAM range is valid
******************************************************************************/
int bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes)
int32_t bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes)
{
uint64_t end = base + size_in_bytes;
int32_t ret = 0;
/*
* Check if the NS DRAM address is valid
*/
if ((base < TEGRA_DRAM_BASE) || (end > TEGRA_DRAM_END)) {
ERROR("NS address is out-of-bounds!\n");
return -EFAULT;
ret = -EFAULT;
}
/*
@ -398,9 +398,9 @@ int bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes)
*/
if ((base < TZDRAM_END) && (end > tegra_bl31_phys_base)) {
ERROR("NS address overlaps TZDRAM!\n");
return -ENOTSUP;
ret = -ENOTSUP;
}
/* valid NS address */
return 0;
return ret;
}

6
plat/nvidia/tegra/include/tegra_private.h
View File

@ -31,9 +31,9 @@ typedef struct plat_params_from_bl2 {
/* TZ memory base */
uint64_t tzdram_base;
/* UART port ID */
int uart_id;
int32_t uart_id;
/* L2 ECC parity protection disable flag */
int l2_ecc_parity_prot_dis;
int32_t l2_ecc_parity_prot_dis;
} plat_params_from_bl2_t;
/*******************************************************************************
@ -90,7 +90,7 @@ int tegra_prepare_cpu_on_finish(unsigned long mpidr);
/* Declarations for tegra_bl31_setup.c */
plat_params_from_bl2_t *bl31_get_plat_params(void);
int bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes);
int32_t bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes);
void plat_early_platform_setup(void);
/* Declarations for tegra_delay_timer.c */