The Arm Generic Timer specification mandates that the
interrupt associated with each timer is low level triggered,
see:
Arm Cortex-A76 Core:
"Each timer provides an active-LOW interrupt output to the SoC."
Arm Cortex-A53 MPCore Processor:
"It generates timer events as active-LOW interrupt outputs and
event streams."
The following files in fdts\
fvp-base-gicv3-psci-common.dtsi
fvp-base-gicv3-psci-aarch32-common.dtsi
fvp-base-gicv2-psci-aarch32.dts
fvp-base-gicv2-psci.dts
fvp-foundation-gicv2-psci.dts
fvp-foundation-gicv3-psci.dts
describe interrupt types as edge rising
IRQ_TYPE_EDGE_RISING = 0x01:
interrupts = <1 13 0xff01>,
<1 14 0xff01>,
<1 11 0xff01>,
<1 10 0xff01>;
, see include\dt-bindings\interrupt-controller\arm-gic.h:
which causes Linux to generate the warnings below:
arch_timer: WARNING: Invalid trigger for IRQ5, assuming level low
arch_timer: WARNING: Please fix your firmware
This patch adds GIC_CPU_MASK_RAW macro definition to
include\dt-bindings\interrupt-controller\arm-gic.h,
modifies interrupt type to IRQ_TYPE_LEVEL_LOW and
makes use of type definitions in arm-gic.h.
Change-Id: Iafa2552a9db85a0559c73353f854e2e0066ab2b9
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
This patch adds support for passing FVP platform's topology
configuration to DTS files for compilation, which allows to
build DTBs with correct number of clusters and CPUs.
This removes non-existing clusters/CPUs from the compiled
device tree blob and fixes reported Linux errors when trying
to power on absent CPUs/PEs.
If DTS file is passed using FVP_HW_CONFIG_DTS build option from
the platform's makefile, FVP_CLUSTER_COUNT, FVP_MAX_CPUS_PER_CLUSTER
and FVP_MAX_PE_PER_CPU parameters are used, otherwise CI script will
use the default values from the corresponding DTS file.
Change-Id: Idcb45dc6ad5e3eaea18573aff1a01c9344404ab3
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
Create, register( and implicitly invoke) fconf_populate_topology()
function which extracts the topology related properties from dtb into
the newly created fconf based configuration structure 'soc_topology'.
Appropriate libfdt APIs are added to jmptbl.i file for use with USE_ROMLIB
build feature.
A new property which describes the power domain levels is added to the
HW_CONFIG device tree source files.
This patch also fixes a minor bug in the common device tree file
fvp-base-gicv3-psci-dynamiq-common.dtsi
As this file includes fvp-base-gicv3-psci-common.dtsi, it is necessary
to delete all previous cluster node definitons because DynamIQ based
models have upto 8 CPUs in each cluster. If not deleted, the final dts
would have an inaccurate description of SoC topology, i.e., cluster0
with 8 or more core nodes and cluster1 with 4 core nodes.
Change-Id: I9eb406da3ba4732008a66c01afec7c9fa8ef59bf
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
Using the /include/ syntax, the include was evaluated by dtc, only after running
the preprocessor, therefore the .dtsi files were not preprocessed. This patch
adds the #include syntax instead. Evaluating this and preprocessing the files
now happens in a single step, done by the C preprocessor.
Change-Id: I6d0104b6274316fc736e84973502a4d6c2c9d6e0
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
RevC models have the MT bit set and the affinities shifted in the MPIDR
register. To make the Linux able to boot all CPUs it needs a modified
DTS file containing the shifted affinity values.
Beside these values the DTS files should be the same so the common part
was moved into a new file which is included in the DTS files with
shifted and non-shifted affinities.
The same setup already exists for 64 bit systems.
Signed-off-by: Imre Kis <imre.kis@arm.com>
Change-Id: I90f7b9c8d8a24c9b3f97232441dbe0a29aa8976d
Alexei Fedorov
Madhukar Pappireddy
Balint Dobszay
Imre Kis