When using SCPI as the PSCI backend, firmware can wake up the CPUs and
cluster from sleep, so CPU idle states are available for the rich OS to
use. In that case, advertise them to the rich OS via the DTB.
Change-Id: I718ef6ef41212fe5213b11b4799613adbbe6e0eb
Signed-off-by: Samuel Holland <samuel@sholland.org>
So far the H616 was the only Allwinner SoC needed to amend the DTB, to
reserve the DRAM portion that BL31 occupies.
To allow other SoCs to modify the DTB as well, without duplicating code,
move the DTB change routines into Allwinner common code, and generalise
the current code to allow other modifications.
No functional change intended.
Change-Id: I080ea07b6470367f3c2573a4368f8ef5196d411c
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
In newer Allwiner SoCs, the AA64nAA32 wires are mapped to a new register
called "General Control Register0" in the manual rather than the
"Cluster 0 Control Register0" in older SoCs.
Now the position of AA64nAA32 (reg and bit offset) is defined in a few
macros instead assumed to be at bit offset 24 of
SUNXI_CPUCFG_CLS_CTRL_REG0.
Change-Id: I933d00b9a914bf7103e3a9dadbc6d7be1a409668
Signed-off-by: Icenowy Zheng <icenowy@sipeed.com>
When the BL31 for the Allwinner H616 runs in DRAM, we need to make sure
we tell the non-secure world about the memory region it uses.
Add a reserved-memory node to the DT, which covers the area that BL31
could occupy. The "no-map" property will prevent OSes from mapping
the area, so there would be no speculative accesses.
Change-Id: I808f3e1a8089da53bbe4fc6435a808e9159831e1
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The new Allwinner H616 SoC lacks the management controller and the secure
SRAM A2, so we need to tweak the memory map quite substantially:
We run BL31 in DRAM. Since the DRAM starts at 1GB, we cannot use our
compressed virtual address space (max 256MB) anymore, so we revert to
the full 32bit VA space and use a flat mapping throughout all of it.
The missing controller also means we need to always use the native PSCI
ops, using the CPUIDLE hardware, as SCPI and suspend depend on the ARISC.
Change-Id: I77169b452cb7f5dc2ef734f3fc6e5d931749141d
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Samuel Holland
Andre Przywara
Icenowy Zheng