2 Commits

Author	SHA1	Message	Date
Konstantin Porotchkin	1e179c7946	plat/marvell: fix SPD handling in dram port ... The DRAM port code issues a dummy write to SPD page-0 i2c address in order to select this page for the forthcoming read transaction. If the write buffer length supplied to i2c_write is not zero, this call is translated to 2 bus transations: - set the target offset - write the data to the target However no actual data should be transferred to SPD page-0 in order to select it. Actually, the second transation never receives an ACK from the target device, which caused the following error report: ERROR: Status 30 in write transaction This patch sets the buffer length in page-0 select writes to zero, leading to bypass the data transfer to the target device. Issuing the target offset command to SPD page-0 address effectively selects this page for the read operation. Change-Id: I4bf8e8c09da115ee875f934bc8fbc9349b995017 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: https://sj1git1.cavium.com/24387 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Ofer Heifetz <oferh@marvell.com> Reviewed-by: Moti Buskila <motib@marvell.com>	2021-02-11 09:43:18 +00:00
Grzegorz Jaszczyk	2c9d263682	plat: marvell: octeontx: add support for t9130 ... CN-9130 has single CP0 inside the package and 2 additional one from MoChi interface. In case of db-9130-modular board the MCI interface is routed to: - on-board CP115 (MCI0) - extension board CP115 (MCI1) The board is based on DIMM DDR. The 9130 has up to 3CP, and decoding windows looks like below: (free for further use) .----------. 0xf800 0000 | CP2 CFG | '----------' 0xf600 0000 | CP1 CFG | '----------' 0xf400 0000 | CP0 CFG | '----------' 0xf200 0000 | AP CFG | '----------' 0xf000 0000 (free for further use) .----------. 0xec00 0000 | SPI | | MEM_MAP | (Currently not opened) '----------' 0xe800 0000 | PEX2_CP2 | '----------' 0xe700 0000 | PEX1_CP2 | '----------' 0xe600 0000 | PEX0-CP2 | '----------' .----------. 0xe500 0000 | PEX2_CP1 | '----------' 0xe400 0000 | PEX1_CP1 | '----------' 0xe300 0000 | PEX0-CP1 | '----------' .----------. 0xe200 0000 | PEX2-CP0 | '----------' 0xe100 0000 | PEX1-CP0 | '----------' 0xe000 0000 | PEX0-CP0 | | 512MB | '----------' 0xc000 0000 Change-Id: Ia8eee4f96c1043753f74f9da437b9f72ce2d6eb0 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>	2020-07-30 15:15:52 +02:00