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7 Commits

Author SHA1 Message Date
Paul Beesley 3441952f61 Merge "intel: agilex: Clear PLL lostlock bypass mode" into integration 2019-08-28 13:05:51 +00:00
Hadi Asyrafi 24d16a2e40 intel: agilex: HMC driver calculate DDR size 
Driver will calculate DDR size instead of using hardcoded value

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I642cf2180929965ef12bd5ae4393b2f3d0dcddde
 2019-08-19 18:19:04 +08:00
Hadi Asyrafi 960a12b3fb intel: agilex: Clear PLL lostlock bypass mode 
To provide glitchless clock to downstream logic even if clock toggles

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I728d64d0ba3b4492125bea5b0737fc83180356f1
 2019-08-19 10:56:31 +08:00
Paul Beesley d1b6013d84 Merge "intel: agilex: Fix memory controller driver" into integration 2019-08-15 15:30:51 +00:00
Hadi Asyrafi b266d82148 intel: agilex: Fix memory controller driver 
Increase calibration delay, fix ddrio control config & nonsecure region
limit

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ibca3c247a3ad5104176ca9057d29755599f13c9b
 2019-08-15 09:28:06 +08:00
Hadi Asyrafi 4e865bd290 intel: agilex: Fix reliance on hard coded clock information 
Extract clock information for UART, MMC & Watchdog from the clock manager

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I42d3d4ceeaf45788d457472f6ddcd3fe099f0133
 2019-08-14 19:06:35 +08:00
Hadi Asyrafi 2f11d548f2 intel: Adds support for Agilex platform 
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ib2ad2068abdf0b204c5cb021ea919581adaca4ef
 2019-07-17 19:06:49 +08:00