Commit Graph

68 Commits

Author SHA1 Message Date
Venkatesh Yadav Abbarapu 302b4dfb8f feat(plat/versal): add support for SLS mitigation
This patch adds the option HARDEN_SLS_ALL that can be used to enable
the -mharden-sls=all, which mitigates the straight-line speculation
vulnerability. Enable this by adding the option HARDEN_SLS_ALL=1,
default this will be disabled.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I0d498d9e96903fcb879993ad491949f6f17769b2
2021-07-20 22:33:47 -06:00
Abhyuday Godhasara fa58171534 fix(plat/xilinx/versal): use sync method for blocking calls
All API calls except non-blocking should wait for
IPI response and read buffer to check return status
from firmware. Some of API calls are not reading
status from IPI payload data. Use sync method which
reads actual return status from IPI payload.

Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: I6f568b85d0da639c264f507122e3015807d8423d
2021-07-08 05:29:50 -07:00
Rajan Vaja e1e5b1339b fix(plat/xilinx/versal/include): correct IPI buffer offset
Use proper offset for IPI data based on offset for IPI0
channel.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: I3070517944dd353c3733aa595df0da030127751a
2021-05-25 07:02:49 -07:00
Venkatesh Yadav Abbarapu 78c7beb49c plat: send an sgi to communicate to linux
Upon recieving the interrupt send an SGI.
The sgi number is communicated by linux.

Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Change-Id: Ib8f07ff7132ba5ac202b546914efb16d04820ed3
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
2021-04-22 22:47:17 +02:00
Shubhrajyoti Datta 8b48bfb897 plat: xilinx: Error management support
Add support for the trapping the IPI in TF-A.
Register handler for the irq no 62 which is the IPI interrupt.

Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Change-Id: I9c04fdae7be3dda6a34a9b196274c0b5fdf39223
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
2021-04-22 22:47:12 +02:00
Venkatesh Yadav Abbarapu 654bd99dc6 plat: xilinx: versal: Add the IPI CRC checksum macro support
Add support for CRC checksum for IPI data when the macro
IPI_CRC_CHECK is enabled.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I3c25c715885759076055c6505471339b5d6edcd5
2021-04-21 12:19:32 +02:00
Venkatesh Yadav Abbarapu 0b25f4045a plat:xilinx:versal: Add JTAG DCC support
As per the new multi-console framework, updating the JTAG DCC support.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: I77994ce387caf0d695986df3d01d414a920978d0
2021-03-31 22:00:21 -06:00
Tejas Patel 4697164a3f plat: xilinx: versal: Mark IPI calls secure/non-secure
BIT24 of IPI command header is used to determine if caller is
secure or non-secure.

Mark BIT24 of IPI command header as non-secure if SMC caller
is non-secure.

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: Iec25af8f4b202093f58e858ee47cd9cd46890267
2021-03-19 07:47:12 -07:00
Michal Simek 4a7b060b3d plat: xilinx: versal: Remove cortex-a53 compilation
Versal is a72 based that's why there is no reason to build low level
assemble code for a53.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: Iff9cf2582102d951825b87fd9af18e831ca717d6
2021-03-16 13:17:37 +01:00
Rajan Vaja f621d5fb4b plat: xilinx: versal: Remove code duplication
Some switch cases uses same operation. So, club switch cases
which uses same operation and remove duplicate code.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I260b474c0ff3f2ca102c32d4af2e4abba2b8f57c
2021-01-20 00:59:33 -08:00
Venkatesh Yadav Abbarapu e43258fa00 plat: xilinx: Fix non-MISRA compliant code
This patch fixes the non compliant code like missing braces for
conditional single statement bodies.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I95b410ae5950f85dc913c4448fcd0a97e0fd490c
2021-01-10 20:48:09 -07:00
Manish Pandey a82b5f70fb xilinx: versal: fix static failure
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Icef550072296d6aba89a0827dd72d0b86047556f
2020-12-10 10:48:22 +00:00
Tejas Patel 6af1228677 plat: xilinx: versal: Add support of register notifier
Add support of register notifier.

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I41ef4c63abcc9aee552790b843adb25a5fd0c23e
2020-12-07 11:10:19 +00:00
Tejas Patel b6d7b3e9d6 plat: xilinx: versal: Add support to get clock rate value
Add support to get clock's rate value.

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I3ed881053ef323b2ca73e13edd0affda860d381d
2020-12-07 11:10:13 +00:00
Tejas Patel 07d8a5f7dc plat: xilinx: versal: Add support of set max latency for the device
Add support of set max latency, to change in the maximum powerup latency
requirements for a specific device currently used by Subsystem.

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I8749886abb1a7884a42c4d156d89c9cd562a5b1a
2020-12-07 11:10:07 +00:00
Ravi Patel 2cc1fa9537 plat: versal: Add InitFinalize API call
Add support to call InitFinalize API in Versal which calls
corresponding LibPM API.

Signed-off-by: Ravi Patel <ravi.patel@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I3428b7245b4db1ef6db8a90b7ad20b6e484ed3b2
2020-12-07 11:10:01 +00:00
Rajan Vaja 1ba2d84fe2 xilinx: versal: Updated Response of QueryData API call
For the current XilPM calls, The handler of IPI returns information
with 16 Bytes data.
So during QueryData API call for the ClockName and PinFunctionName,
response data(name of clock or function) response[0..3] are used to
return name. And status is not being returned for such API.

Updated XilPM calls reply in a consistent way and The handler of IPI
return information with 32Bytes data. Where response[0] always set
to status.
For the version-2 of QueryData API, during call for the ClockName
and PinFunctionName, response data(name of clock or function) get as
response[1...4].

To support both the version of QueryData API, added version based
compatibility by the use of feature check.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Signed-off-by: Amit Sunil Dhamne <amit.sunil.dhamne@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I336128bff7bbe659903b0f8ce20ae6da7e3b51b4
2020-12-07 11:09:56 +00:00
Venkatesh Yadav Abbarapu abf27efac6 plat:xilinx:versal: Use defaults when PDI is without sw partitions
In JTAG mode check the ATF handoff structure, if the magic string
is not present then use bl32 and bl33 default values.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I1f2c4a2060d8a2e70d3b5fb2473124b685f257fc
2020-12-07 11:09:47 +00:00
Ravi Patel d4c7b55050 xilinx: versal: Skip store/restore of GIC during CPU idle
GIC registers needs to be stored/restored during system
suspend/resume only and not during CPU idle.
During CPU idle, minimum 1 CPU is in ON state.

Signed-off-by: Ravi Patel <ravi.patel@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I5de2ce3a61bf4260f9385349202b0f592a47aaba
2020-12-07 11:07:41 +00:00
Venkatesh Yadav Abbarapu 4b8ab607ea plat: versal: Update API list in feature check
Add below API in feature check list which is actually present in
firmware:
- PM_GET_CHIPID

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Signed-off-by: Ravi Patel <ravi.patel@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I98b82da74164f065c8835861f74b0f2855e9bcbf
2020-12-07 11:07:32 +00:00
Ravi Patel b05d2792ae xilinx: versal: Do not pass ACPU0 always in set_wakeup_source()
Existing code passes ACPU0 to LibPM as node_id in set_wakeup_source()
call because last suspending core will be ACPU0 in most of the case.

Now it may be possible that user may disable the ACPU0 using hot-plug
and after that it suspends Linux. So in that case ACPU0 will not be
last suspending core.

To overcome above scenario, pass the current running processor ID
while calling set_wakeup_source().

Signed-off-by: Ravi Patel <ravi.patel@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: If15354c2150b5bb1305b5f93ca4e8c7a81d59f0a
2020-12-07 11:07:24 +00:00
Olivier Deprez 8eceb1c9c4 Merge "Create separate header for ARM specific SMCCC defines" into integration 2020-03-31 14:16:40 +00:00
Manish V Badarkhe 53adebad8b Create separate header for ARM specific SMCCC defines
Moved SMCCC defines from plat_arm.h to new <smccc_def.h> header
and include this header in all ARM platforms.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I4cbc69c7b9307461de87b7c7bf200dd9b810e485
2020-03-30 12:21:38 +00:00
Alexei Fedorov a6ea06f563 TF-A GICv3 driver: Introduce makefile
This patch moves all GICv3 driver files into new added
'gicv3.mk' makefile for the benefit of the generic driver
which can evolve in the future without affecting platforms.
The patch adds GICv3 driver configuration flags
'GICV3_IMPL', 'GICV3_IMPL_GIC600_MULTICHIP' and
'GICV3_OVERRIDE_DISTIF_PWR_OPS' described in
'GICv3 driver options' section of 'build-option.rst'
document.

NOTE: Platforms with GICv3 driver need to be modified to
include 'drivers/arm/gic/v3/gicv3.mk' in their makefiles.

Change-Id: If055f6770ff20f5dee5a3c99ae7ced7cdcac5c44
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2020-03-30 10:54:01 +00:00
Alexei Fedorov 6e19bd563d TF-A GICv3 driver: Separate GICD and GICR accessor functions
This patch provides separation of GICD, GICR accessor
functions and adds new macros for GICv3 registers access
as a preparation for GICv3.1 and GICv4 support.
NOTE: Platforms need to modify to include both
'gicdv3_helpers.c' and 'gicrv3_helpers.c' instead of the
single helper file previously.

Change-Id: I1641bd6d217d6eb7d1228be3c4177b2d556da60a
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2020-03-10 09:40:19 +00:00
Andre Przywara f695e1e01a pl011: Use generic console_t data structure
Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data structure at all.

Change-Id: I7a23327394d142af4b293ea7ccd90b843c54587c
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2020-02-25 09:34:38 +00:00
Tejas Patel 932f8b477b xilinx: versal: Pass result count to pm_get_callbackdata()
pm_get_callbackdata() expect result count and not total bytes of
result. Correct it by passing result count to pm_get_callbackdata().

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I01ce0002f7a753e81ea9fe65edde8420a13ed51a
2020-01-30 11:31:52 -08:00
Deepika Bhavnani 6cdef9ba11 xilinx: Unify Platform specific defines for PSCI module
PLATFORM_CORE_COUNT - Unsigned int
PLATFORM_CLUSTER_COUNT - Unsigned int
PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int
PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int

Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com>
Change-Id: I76f5535f1cbdaf3fc1235cd824111d9afe8f7e1b
2020-01-24 10:02:15 -06:00
Venkatesh Yadav Abbarapu 31ce893ec2 xilinx: versal: PLM to ATF handover
Parse the parameter structure the PLM populates, to populate the
bl32 and bl33 image structures.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I317072d1086f6cc6f90883c1b8b6d086ff57b443
2020-01-23 03:01:22 -07:00
Tejas Patel 92c30ac35b plat: xilinx: Move pm_client.h to common directory
Move pm_client.h to common directory to avoid duplication
of function declaration.

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Iea542e681f42db089cccd9b24d286ac8f0a2ce35
2020-01-15 11:04:15 -08:00
Siva Durga Prasad Paladugu 7b9f0cfd8c plat: xilinx: versal: Make silicon default build target
This patch makes default build target as silicon instead of QEMU.
The default can be overwritten by specifying it through build flag
VERSAL_PLATFORM.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Ia4cb1df1f206db3e514e8ce969acca875e973ace
2020-01-15 11:04:10 -08:00
Siva Durga Prasad Paladugu d69bbd0e80 xilinx: versal: Wire silicon default setup
Add new option for serial and default clock setup.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I0ca7ad51637cdaa6bb891f22c53595d20da7236a
2020-01-15 11:04:05 -08:00
Venkatesh Yadav Abbarapu 29af478975 versal: Increase OCM memory size for DEBUG builds
ATF can't fit in current OCM size when the DEBUG is enabled, so
increase the OCM size to use 128Kb.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I2ebfd1f2e9db9c0b28770aea7f8fbf1a8a15787a
2020-01-15 11:04:00 -08:00
Siva Durga Prasad Paladugu f8a650c153 plat: xilinx: versal: Dont set IOU switch clock
The IOU switch clock will be set by PLM during boot so there is no need to
set here and hence this patch removes it.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I1512708411eb07a07c1a8fbd66575efee975431a
2020-01-15 11:03:56 -08:00
Siva Durga Prasad Paladugu c959c479eb arm64: versal: Adjust cpu clock for versal virtual
This patch modifies cpu clock for Xilinx Versal virtual
platform in order to keep same as used by QEMU.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I169d082462d7ce94a82c62966ab9eb122c5a3fee
2020-01-15 11:03:52 -08:00
Saeed Nowshadi f50828d52e xilinx: versal: Add support for PM_GET_OPERATING_CHARACTERISTIC EEMI call
This patch adds EEMI support for PM_GET_OPERATING_CHARACTERISTIC api id.  This
interface obtains operating characteristic of a device from PMC firmware.  The
'power', 'temperature', and 'latency' characteristic are the options that are
supported.

Signed-off-by: Saeed Nowshadi <saeed.nowshadi@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: If30959ba6a3a778a17df2a4281c2c09832cf7e92
2020-01-15 11:03:47 -08:00
Ravi Patel ea6e1c3942 plat: versal: Add Get_ChipID API
Add support for Get_ChipID API in Versal which calls corresponding
LibPM API.

Signed-off-by: Ravi Patel <ravi.patel@xilinx.com>
Acked-by: Jolly Shah <jolly.shah@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I25c4b301721d7989d982ac376c59195c55564022
2020-01-15 11:03:43 -08:00
Jolly Shah e4c54c0d2d plat: xilinx: versal: Add load Pdi API support
This patch adds support for load pdi api to enable loading
pdi from linux.

Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I48549e276e1f7b9be45a0bebf559f73bd09d5f69
2020-01-15 11:03:38 -08:00
Ravi Patel 39db98efc9 xilinx: versal: Add feature check API
Add API to check availability of given API in ATF
as well as platform management controller and returns
the supported version number.

Signed-off-by: Ravi Patel <ravi.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I608b38f60b36c4d105b7a205ecb8b02de0c00f3c
2020-01-15 11:03:34 -08:00
Tejas Patel 6e82cd8c9b xilinx: versal: Implement set wakeup source for client
Add support to set wakeup source for APU while suspending.

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I4809fd83a710def8144fdad74990c45e62b8fdf3
2020-01-15 11:03:30 -08:00
Rajan Vaja 89224531b4 plat: xilinx: versal: Add GET_CALLBACK_DATA function
Add GET_CALLBACK_DATA function to get IPI callback
data in Linux during init suspend callback.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Ieb60e561b5f656611f0702c43ba6a4296a012651
2020-01-15 11:03:26 -08:00
Saeed Nowshadi 0abf4bba50 xilinx: versal: Add PSCI APIs for system shutdown & reset
Add following APIs in plat_psci to support system shutdown & reset:
- versal_system_off
- versal_system_reset

Signed-off-by: Saeed Nowshadi <saeed.nowshadi@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Ia2c1a19ded18984b393e1fdee760bf48b45e9902
2020-01-15 11:03:20 -08:00
Tejas Patel 5a8ffeabf9 xilinx: versal: Add PSCI APIs for suspend/resume
Add following APIs in plat_psci to support suspend resume:
- versal_pwr_domain_off
- versal_pwr_domain_suspend
- versal_pwr_domain_suspend_finish
- versal_validate_power_state
- versal_get_sys_suspend_power_state

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Ife908a45f32e2037c9c19e13211a8e4b373b8342
2020-01-15 11:03:16 -08:00
Tejas Patel 394a65aa96 xilinx: versal: Remove no_pmc ops to ON power domain
Add PMC ops for power domain ON and remove no_pmc ops.

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Id4308dfe124b60a751765beb3397d1b0071f14fc
2020-01-15 11:03:10 -08:00
Tejas Patel 42cd77e386 xilinx: versal: Add set wakeup source API
Implement set wakeup source API to pass SMC
call for set wakeup source to PLM (Platform Loader
and Manager).

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I654ce07235c0fc7dfcb81bf98820153255f61537
2020-01-15 11:03:06 -08:00
Tejas Patel 25b1a91033 xilinx: versal: Add client wakeup API
Implement client wakeup API for versal.

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I31b1b362fe645a82f89ce2d698ee71eb00cf15dc
2020-01-15 11:03:02 -08:00
Tejas Patel 1f71e4fbfe xilinx: versal: Add query data API
Add PM_QUERY_DATA API to pass query data
EEMI call from Linux to PLM .

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I18735b72ab9cb62fb6cbc7582e77de6cb57f99b0
2020-01-15 11:02:58 -08:00
Tejas Patel c56be55df3 xilinx: versal: Add request wakeup API
Implement request wakeup API for versal.

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I40a2a4ea85bf05623ac8a17ef4a6fa329babd27e
2020-01-15 11:02:54 -08:00
Tejas Patel ad19911c72 xilinx: versal: Add PM_INIT_FINALIZE API for versal
PM_INIT_FINALIZE is not required for versal. To use Linux
Zynqmp PM driver for versal, handle PM_INIT_FINALIZE API
in ATF for versal by always returning SUCCESS.

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I6fe5445d78e713d70282ac8931ff8b17c96b2a14
2020-01-15 11:02:50 -08:00
Tejas Patel 4b0f32a411 xilinx: versal: Add support of PM_GET_TRUSTZONE_VERSION API
PM_GET_TRUSTZONE_VERSION API is required to use zynqmp-firmware
driver for versal. Add support of PM_GET_TRUSTZONE_VERSION API
for versal.

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Ie1c859890096024cc8be67386e3fd0f5f8a4385f
2020-01-15 11:02:43 -08:00