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3 Commits

Author SHA1 Message Date
Manoj Kumar 4af5397753 feat(morello): add changes to enable TBBR boot 
This patch adds all SOC and FVP related changes required to boot
a standard TBBR style boot on Morello.

Signed-off-by: sahil <sahil@arm.com>
Change-Id: Ib8f7f326790b13082cbe8db21a980e048e3db88c
 2021-12-16 19:55:08 +05:30
Manoj Kumar 2d39b39704 feat(morello): zero out the DDR memory space 
For Morello SoC, we use ECC capability for the RDIMMs
which require the entire DDR memory space to be zeroed
out before it can be accessed.

Change-Id: Icbe9916f9a2d3c4ce839d8bf7f867efa18f33e23
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
 2021-12-15 11:50:29 +05:30
Chandni Cherukuri dfd5bfb097 plat/arm: Add platform support for Morello 
This patch adds support for Morello platform.
It is an initial port which includes only BL31 support
as the System Control Processor (SCP) is expected to take
the role of primary bootloader.

Change-Id: I1ecbe5a14a2d487b2ecea3c1ca227f08473ed2dd
Co-authored-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Signed-off-by: Anurag Koul <anurag.koul@arm.com>
 2020-09-28 19:33:24 +05:30