Commit Graph

11 Commits

Author SHA1 Message Date
Sieu Mun Tang 77902fca8f feat(intel): add SMC support for ROM Patch SHA384 mailbox
HSD #16014059592:
Add support for ROM Patch SHA384 mailbox SMC call.

Signed-off-by: Kris Chaplin <kris.chaplin@linux.intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ide9a7af41a089980745cb7216a9bf85e7fbd84e3
2022-04-05 14:23:26 +08:00
Sieu Mun Tang f571183b06 fix(intel): make FPGA memory configurations platform specific
Define FPGA_CONFIG_SIZE and FPGA_CONFIG_ADDR in
platform-specific header. This is due to different
allocated sizes between platforms.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Iac4fbf4d4940cdf31834a9d4332f9292870dee76
2022-03-09 09:14:21 +08:00
Sieu Mun Tang c703d752cc fix(intel): fix ECC Double Bit Error handling
SError and Abort are handled in Linux (EL1) instead of
EL3. This patch adds some functionality that complements the
use cases by Linux as follows:

- Provide SMC for ECC DBE notification to EL3
- Determine type of reset needed and service the request in
  place of Linux

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I43d02c77f28004a31770be53599a5a42de412211
2022-03-09 09:14:16 +08:00
Sieu Mun Tang 286b96f4bb build(intel): initial commit for crypto driver
This patch adds driver for Intel FPGA's Crypto Services.
These services are provided by Intel platform
Secure Device Manager(SDM) and are made accessible by
processor components (ie ATF).
Below is the list of enabled features:
- Send SDM certificates
- Efuse provision data dump
- Encryption/decryption service
- Hardware IP random number generator

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: If7604cd1cacf27a38a9a29ec6b85b07385e1ea26
2022-03-09 09:13:20 +08:00
Abdul Halim, Muhammad Hadi Asyrafi aad868b4d9 intel: common: Change how mailbox handles job id & buffer
This patch modifies several basic mailbox driver features to prepare for
FCS enablement:
- Job id management for asynchronous response
- SDM command buffer full

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I78168dfb6c521d70d9cba187356b7a3c8e9b62d2
2020-10-27 11:17:34 +08:00
Richard Gong 1ae7b6f6b1 intel: SIP: increase FPGA_CONFIG_SIZE to 32 MB
Increase INTEL_SIP_SMC_FPGA_CONFIG_SIZE from 16 to 32MB. We need higher
pre-reserved memory size between Intel service layer and secure monitor
software so we can handle JIC file authorization.

Signed-off-by: Richard Gong <richard.gong@intel.com>
Change-Id: Ibab4e42e4b7b93a4cf741e60ec9439359ba0a64c
2020-10-24 11:00:42 +08:00
Abdul Halim, Muhammad Hadi Asyrafi 516f32219b intel: common: Clean up mailbox and sip header
Sort and rearrange definitions in both mailbox and sip header to
increase readability and maintainability.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I5544c2f17efdf3174757c55afd8cc1062fbae856
2020-10-24 11:00:42 +08:00
Abdul Halim, Muhammad Hadi Asyrafi 960896eb89 intel: Update RSU driver return code
Modify RSU driver error code for backward-compatibility with
Linux RSU driver

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ib9e38d4017efe35d3aceeee27dce451fbd429fb5
2020-02-27 20:25:58 +08:00
Hadi Asyrafi 0c5d62ad7f intel: Introduce SMC support for mailbox command
This update allows normal world to send mailbox commands through SMC

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I587bea06422da90e5907d586495cd9e3bde900f6
2020-02-05 16:26:15 +08:00
Tien Hock, Loh cefb37eb39 plat: intel: Fix FPGA manager on reconfiguration
Fixes the SiP Service driver that is responsible for FPGA
reconfiguration. Also change the base address of FPGA reconfiguration
to 0x400000.

Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com>
Change-Id: I2b84c12c85cd5fc235247131fec4916ed2fb56c8
2019-12-17 19:45:24 +08:00
Hadi Asyrafi d25041bf1e intel: Create SiP service header file
Separate SiP related definition from mailbox header file

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I45ba540f29d9261007f7ec23469358747cf140b4
2019-12-17 10:17:47 +08:00