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9 Commits

Author SHA1 Message Date
Chee Hong Ang 7f56f240d3 intel: clear 'PLAT_SEC_ENTRY' in early platform setup 
Ensure 'PLAT_SEC_ENTRY' is cleared during early platform
setup. This is to prevent the slave CPU cores jump to the stale
entry point after warm reset when using U-Boot SPL as first
stage boot loader.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Change-Id: I3294ce2f74aa691d0cf311fa30f27f9d4fb8800a
 2020-10-24 11:00:42 +08:00
Tien Hock, Loh d603fd3033 intel: Enable EMAC PHY in Intel FPGA platform 
This initializes the EMAC PHY in both Stratix 10 and Agilex,
without this, EMAC PHY wouldn't work correctly.

Change-Id: I7e6b9e88fd9ef472884fcf648e6001fcb7549ae6
Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
 2020-02-25 10:19:51 +08:00
Deepika Bhavnani dc2d366fac intel: Unify Platform specific defines for PSCI module 
PLATFORM_CORE_COUNT - Unsigned int
PLATFORM_CLUSTER_COUNT - Unsigned int
PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int
PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int

Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com>
Change-Id: Id3d3efc7e7711d19f0223da823713b8390ad2f47
 2020-01-24 13:15:11 +00:00
Tien Hock, Loh 389091a8d6 plat: intel: Fix UEFI decompression issue 
UEFI decompression will fail if the payload size is too large and the load
address is too low. This patch moves the payload to a higher address to fix
the issue

Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com>
Change-Id: I36087fbd2237b62891c59dbe2d34336bddfaa396
 2020-01-15 13:41:34 +00:00
Hadi Asyrafi 32cf34acac intel: Implement platform specific system reset 2 
Add support for platform specific warm-reset through psci system reset 2.

- system_reset2 implementation that calls for l2 cache reset
- Check for magic number and request for warm reset in bl2
- Create a shared reset manager header file for Agilex and Stratix 10
- Clean up parameter info in plat_get_next_bl_params

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I3fdd9a2711c80d9bd3dc05b81527781d840bd726
 2019-12-30 10:17:04 +08:00
Hadi Asyrafi 23f31d39bf intel: stratix10: Modify BL31 parameter handling 
Add-in support for handling BL31 parameter from non-BL2 image, ie. SPL

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I16118d791399f652b6d1093c10092935a3449c32
 2019-12-17 12:54:34 +08:00
Hadi Asyrafi cf82aff098 intel: Modify BL31 address mapping 
Load BL31 to DDR instead of On-Chip RAM for scalability. Also, make use
of On-Chip RAM for BL31 specific variables filling down from handoff
offset to reduce fragmentation

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ib64f48bd14f71e5fca2d406f4ede3386f2881099
 2019-12-17 12:54:34 +08:00
Hadi Asyrafi 2db1e7663d intel: stratix10: Enable uboot entrypoint support 
This patch will provide an entrypoint for uboot's spl into BL31.
BL31 will also handle secondary cpu state during uboot's cold boot

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I661bdb782c2d793d5fc3c7f78dd7ff746e33b7a3
 2019-12-17 12:54:29 +08:00
Hadi Asyrafi 328718f254 intel: Refactor common platform code [1/5] 
Pull out handoff driver to intel/soc/ common directory as they can be
shared by both Agilex and Stratix10 platform.

Share platform_def header between both Agilex and Stratix10 and store
platform specific definitions in socfpga_plat_def.h

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I8eff1afd7ee71704a36a54fad732ede4f557878d
 2019-11-28 12:47:57 +08:00