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3 Commits

Author SHA1 Message Date
Jiafei Pan 35efe7a4ce feat(plat/nxp/common): define common macro for ARM registers 
Define common register macro both for Cortex-A53 and Cortex-A72
because the code will be used by both Cortex platform.

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I485661bfe3ed4f214c403ff6af53dc6af1ddf089
 2021-09-15 11:19:36 +08:00
Jiafei Pan 08695df91d refactor(plat/nxp): refine api to read SVR register 
1. Refined struct soc_info_t definition.
2. Refined get_soc_info function.
3. Fixed some SVR persernality value.
4. Refined API to get cluster numbers and cores per cluster.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I3c20611a523516cc63330dce4c925e6cda1e93c4
 2021-08-26 10:08:57 +08:00
Pankaj Gupta b53c2c5f2d nxp: platform files for bl2 and bl31 setup 
For NXP platforms:
- Setup files for BL2 and BL31
- Other supporting files.

Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I36a1183a0652701bdede9e02d41eb976accbb017
 2021-03-24 09:49:32 +05:30