Extract clock information for UART, MMC & Watchdog from the platform
rather than hard code it
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I2582bd34a6da97bd75d5ccba5f93840e65f26b03
Pull out common code from aarch64 and include
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I4d0f5e1bb01bcdacbedf8e6c359de594239b645f
Watchdog driver support & enablement during platform setup
Signed-off-by: Muhammad Hadi Asyrafi Abdul Halim <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Manages QSPI initialization, configuration and IO handling as boot device
Signed-off-by: Muhammad Hadi Asyrafi Abdul Halim <muhammad.hadi.asyrafi.abdul.halim@intel.com>
MMC stack needs OCR voltage information for the platform to initialize
MMC controller correctly.
Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com>
Change map region for device 2 from non-secure to secure
Signed-off-by: Muhammad Hadi Asyrafi Abdul Halim <muhammad.hadi.asyrafi.abdul.halim@intel.com>
A DDR calibration value is missing write mask, causing ECC DDR calibration
to fail. This patch addresses the issue. ECC should also be scrubbed before
MMU initializes, thus the scrubbing is moved to ddr intialization phase.
Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>