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4 Commits

Author SHA1 Message Date
Sandrine Bailleux 5119fa7b8d Merge changes from topic "intel-plat-refactor" into integration 
* changes:
  intel: Platform common code refactor
  intel: Platform common code refactor
 2019-08-07 14:20:01 +00:00
Hadi Asyrafi 3f7b1490dc intel: Platform common code refactor 
Pull out common code from aarch64 and include

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I4d0f5e1bb01bcdacbedf8e6c359de594239b645f
 2019-08-07 12:19:11 +00:00
Hadi Asyrafi 600db4e338 intel: stratix10: Fix BL31 memory mapping 
Previous config blocks ATF runtime service communications with SDM mailbox

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ia857facd0bd0790056df94ed1e016bcf619a161e
 2019-08-02 20:16:32 +08:00
Tien Hock, Loh 1cf55aba49 plat: intel: Add BL31 support to Intel Stratix10 SoCFPGA platform 
This adds BL31 support to Intel Stratix10 SoCFPGA platform. BL31 in TF-A
supports:
- PSCI calls to enable 4 CPU cores
- PSCI mailbox calls for FPGA reconfiguration

Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>
 2019-02-26 09:25:14 +08:00