Commit Graph

3 Commits

Author SHA1 Message Date
Hadi Asyrafi 960a12b3fb intel: agilex: Clear PLL lostlock bypass mode
To provide glitchless clock to downstream logic even if clock toggles

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I728d64d0ba3b4492125bea5b0737fc83180356f1
2019-08-19 10:56:31 +08:00
Hadi Asyrafi 4e865bd290 intel: agilex: Fix reliance on hard coded clock information
Extract clock information for UART, MMC & Watchdog from the clock manager

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I42d3d4ceeaf45788d457472f6ddcd3fe099f0133
2019-08-14 19:06:35 +08:00
Hadi Asyrafi 2f11d548f2 intel: Adds support for Agilex platform
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ib2ad2068abdf0b204c5cb021ea919581adaca4ef
2019-07-17 19:06:49 +08:00