Commit Graph

3 Commits

Author SHA1 Message Date
Hadi Asyrafi f2decc7690 intel: Add function to check fpga readiness
Create a function to check for fpga readiness, and move the checking out
of bridge enable function.

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I3f473ffeffa9ce181a48977560c8bda19c6123c0
2020-01-16 10:56:43 +08:00
Hadi Asyrafi 20335ca8d5 intel: System Manager refactoring
Refactored system manager driver to be shared across both intel platform

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ic4d056c3d15c3152403dc11641c2452770a6162d
2020-01-16 10:53:26 +08:00
Hadi Asyrafi 391eeeef7f intel: Refactor reset manager driver
Refactor reset manager into intel common platform directory as it can be
shared by both Stratix 10 and Agilex. Register address and field is now
referred through macros.

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Id6d50f2a2f5a6bd8d6746b84602ac17ec7f6c07a
2020-01-16 10:53:23 +08:00