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9 Commits

Author SHA1 Message Date
Jiafei Pan 602cf53b6f feat(layerscape): add soc helper macro definition for chassis 3 
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I27b3a1f597de84dc2a007798e54eb919c877281a
 2022-03-27 23:24:24 +08:00
Jiafei Pan 0d396d6455 feat(layerscape): define more chassis 3 hardware address 
Add base address definiton for Chassis 3 platforms.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I6041b93c9e9bb49af60743bd277ac7cc6f1b9da8
 2022-03-27 23:24:24 +08:00
Jiafei Pan b759727f59 feat(nxp/common/io): add ifc nor and nand as io devices 
Added IFC Nor and NAN flash as boot IO devices.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Ie1b87174d9c08d4e32138066b007fef6f8e3c5dd
 2022-01-20 23:38:03 +08:00
Jiafei Pan d374060abe feat(nxp/common/rcpm): add RCPM2 registers definition 
Added some RCPM2 register offset definiton for register: IPSTPCR,
IPSTPACKR and POWMGTDCR, also added OVRD bit definiton of register
POWMGTDCR.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I301bc1401e053c2089b5eb3672c6e649c805a2ab
 2022-01-19 11:36:23 +08:00
Jiafei Pan 8bfb16813a feat(plat/nxp/common): add EESR register definition 
Add OCRAM bit mask to be used in OCRAM driver.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: If82542cc6c1c243d8f998b193954dd72312ee1a4
 2021-10-09 10:57:46 +02:00
Jiafei Pan 4225ce8b87 feat(plat/nxp/common): define default SD buffer 
Define default SD buffer address and size in DRAM.

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I5872d95b0c1114e05f0e145756e9a6ef39b2fd9a
 2021-09-15 11:28:47 +08:00
Jiafei Pan 66f7884b52 feat(plat/nxp/common): add SecMon register definition for ch_3_2 
Add SecMon register definition for ch_3_2.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I80d134ea4e94ad234e1a8fbd02798d5fd86d2544
 2021-09-15 11:19:36 +08:00
Jiafei Pan 6cad59c429 feat(plat/nxp/common): add CCI and EPU address definition 
Add CCI and EPU base address definiton for Chassis v3.2.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I13250555b6646c1e7ba2e9d7c9efca8501f17b3a
 2021-09-15 11:19:36 +08:00
Pankaj Gupta dc05e50b8d nxp: deflt hdr files for soc & their platforms 
- Default header files for:
  -- plat/nxp/soc-lxxxx/include/soc.h uses:
	--- soc_default_base_addr.h
        --- soc_default_base_macros.h

  -- plat/nxp/soc-lxxxx/<$PLAT>/platform_def.h uses:
	--- plat_default_def.h: Every macro define can be overidden.

  -- include/common/tbbr/tbbr_img_def.h uses:
	--- plat_tbbr_img_def.h: platform specific new FIP image macros.

Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: Ic50003e27e87891be3cd18bdb4e14a1c7272d492
 2021-03-24 09:49:32 +05:30