This change replaces hdlcd with DPU in dts file for TC0
Change-Id: If25dfd3ddffc07279ab487f65e1bb82b27a26604
Signed-off-by: Avinash Mehta <avinash.mehta@arm.com>
This includes both cpu and cluster sleep parameters.
Change-Id: I6a9e90b88508d6d2acd2538007cbbdd1cf976442
Signed-off-by: Usama Arif <usama.arif@arm.com>
The pl180 mmc uses 3.3V fixed regulator and vexpress
sysreg for card detection and write protect.
Change-Id: I2513cfcb97217e282a081a700f3a9f723e8207ff
Signed-off-by: Usama Arif <usama.arif@arm.com>
This patch adds support for Total Compute (TC0) platform. It is an
initial port and additional features are expected to be added later.
TC0 has a SCP which brings the primary Cortex-A out of reset
which starts executing BL1. TF-A optionally authenticates the SCP
ram-fw available in FIP and makes it available for SCP to copy.
Some of the major features included and tested in this platform
port include TBBR, PSCI, MHUv2 and DVFS.
Change-Id: I1675e9d200ca7687c215009eef483d9b3ee764ef
Signed-off-by: Usama Arif <usama.arif@arm.com>
Avinash Mehta
Usama Arif