31 lines
1.5 KiB
ReStructuredText
31 lines
1.5 KiB
ReStructuredText
Maximum Power Mitigation Mechanism (MPMM)
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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|MPMM| is an optional microarchitectural power management mechanism supported by
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some Arm Armv9-A cores, beginning with the Cortex-X2, Cortex-A710 and
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Cortex-A510 cores. This mechanism detects and limits high-activity events to
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assist in |SoC| processor power domain dynamic power budgeting and limit the
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triggering of whole-rail (i.e. clock chopping) responses to overcurrent
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conditions.
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|MPMM| is enabled on a per-core basis by the EL3 runtime firmware. The presence
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of |MPMM| cannot be determined at runtime by the firmware, and therefore the
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platform must expose this information through one of two possible mechanisms:
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- |FCONF|, controlled by the ``ENABLE_MPMM_FCONF`` build option.
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- A platform implementation of the ``plat_mpmm_topology`` function (the
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default).
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See :ref:`Maximum Power Mitigation Mechanism (MPMM) Bindings` for documentation
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on the |FCONF| device tree bindings.
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.. warning::
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|MPMM| exposes gear metrics through the auxiliary |AMU| counters. An
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external power controller can use these metrics to budget SoC power by
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limiting the number of cores that can execute higher-activity workloads or
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switching to a different DVFS operating point. When this is the case, the
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|AMU| counters that make up the |MPMM| gears must be enabled by the EL3
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runtime firmware - please see :ref:`Activity Monitor Auxiliary Counters` for
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documentation on enabling auxiliary |AMU| counters.
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