Varun Wadekar 6a1c17c770 feat(gic600ae_fmu): enable all GICD, PPI, ITS SMs ... The following SMIDs are disabled by default. * GICD: MBIST REQ error and GICD FMU ClkGate override * PPI: MBIST REQ error and PPI FMU ClkGate override * ITS: MBIST REQ error and ITS FMU ClkGate override This patch explicitly enables them during the FMU init sequence. Change-Id: I573e64786e3318d4cbcd07d0a1caf25f8e6e9200 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>		2022-04-07 15:21:40 +02:00
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arm_gicv3_common.c	Sanitise includes across codebase	2019-01-04 10:43:17 +00:00
gic-x00.c	refactor(gic): move GIC IIDR numbers	2021-09-01 12:50:08 +01:00
gic600_multichip.c	fix: remove "experimental" tag for stable features	2021-10-22 10:49:20 +01:00
gic600_multichip_private.h	feat(gicv3): multichip: detect GIC-700 at runtime	2021-09-01 16:14:03 +01:00
gic600ae_fmu.c	feat(gic600ae_fmu): enable all GICD, PPI, ITS SMs	2022-04-07 15:21:40 +02:00
gic600ae_fmu_helpers.c	feat(gic600ae_fmu): disable SMID for unavailable blocks	2022-04-07 10:00:23 +02:00
gicdv3_helpers.c	TF-A GICv3 driver: Add extended PPI and SPI range	2020-04-06 16:27:54 +01:00
gicrv3_helpers.c	TF-A GICv3 driver: Change API for GICR_IPRIORITYR accessors	2020-04-07 18:40:44 +01:00
gicv3.mk	feat(gic600ae): introduce support for Fault Management Unit	2021-09-01 08:24:33 -07:00
gicv3_helpers.c	feat(gicv3): introduce GIC component identification	2021-11-04 15:58:34 +00:00
gicv3_main.c	feat(gicv3): detect GICv4 feature at runtime	2021-09-01 16:14:03 +01:00
gicv3_private.h	fix(gicv3): fix iroute value wrong issue	2021-12-06 17:38:39 +01:00