Chandni Cherukuri 0e27faf484 plat/arm/common: add an additional platform power level ... For platforms using multi-threaded CPUs, there can be upto four platform power domain levels. At present, there are three platform power domain levels that are defined for the CSS platforms. Define a fourth level 'ARM_PWR_LVL3' as well to provide support for an additional platform power domain level. Change-Id: I40cc17a10f4690a560776f504364fd7277a7e72a Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>		2018-11-27 10:32:55 +05:30
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aarch64	Standardise header guards across codebase	2018-11-08 10:20:19 +00:00
arm_config.h	Standardise header guards across codebase	2018-11-08 10:20:19 +00:00
arm_def.h	plat/arm/common: add an additional platform power level	2018-11-27 10:32:55 +05:30
arm_dyn_cfg_helpers.h	plat/arm: Fix MISRA defects in dyn config	2018-11-01 14:15:39 +00:00
arm_reclaim_init.ld.S	FVP: Reclaim init code for the stack	2018-10-03 12:06:07 +01:00
arm_sip_svc.h	plat/arm: Fix MISRA defects in SiP SVC handler	2018-10-29 14:41:48 +00:00
arm_spm_def.h	Standardise header guards across codebase	2018-11-08 10:20:19 +00:00
arm_tzc_dram.ld.S	FVP: Reclaim init code for the stack	2018-10-03 12:06:07 +01:00
plat_arm.h	plat/arm: Fix MISRA defects in SiP SVC handler	2018-10-29 14:41:48 +00:00