Ravi Patel 138cde662f zynqmp: pm: Add CLK_SET_RATE_PARENT in gem clock node ... Existing implementation does not allow to change the value of the DIV1 because DIV2 does not have SET_RATE_PARENT flag. This causes DIV1 value to be fixed and only value of DIV2 will be adjusted according to required clock rate. Signed-off-by: Ravi Patel <ravi.patel@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Change-Id: Ic6c4ca091bf0c5dc91ebddf86621c82c705dc87b		2020-01-14 16:26:29 -08:00
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aarch64	plat: xilinx: zynqmp: Correct syscnt freq for QEMU	2020-01-07 15:01:28 -08:00
include	zynqmp: pm: Add LPD WDT clock to the pm_clock structure	2020-01-07 15:03:43 -08:00
ipi_mailbox_service	Move generic ipi_mb functions to common files	2019-01-09 12:15:10 -08:00
pm_service	zynqmp: pm: Add CLK_SET_RATE_PARENT in gem clock node	2020-01-14 16:26:29 -08:00
tsp	zynqmp: add support for multi console interface	2019-07-01 11:35:34 +05:30
bl31_zynqmp_setup.c	zynqmp: add support for multi console interface	2019-07-01 11:35:34 +05:30
plat_psci.c	plat/arm: Sanitise includes	2019-01-25 16:04:10 +00:00
plat_startup.c	plat: xilinx: zynqmp: Move zynqmp_private.h to include directory	2019-01-09 12:05:13 -08:00
plat_topology.c	Use SPDX license identifiers	2017-05-03 09:39:28 +01:00
plat_zynqmp.c	plat: xilinx: zynqmp: Move zynqmp_private.h to include directory	2019-01-09 12:05:13 -08:00
platform.mk	plat: xilinx: zynqmp: Initialize IPI table from zynqmp_config_setup()	2019-09-10 12:25:56 -07:00
sip_svc_setup.c	plat: xilinx: zynqmp: Initialize IPI table from zynqmp_config_setup()	2019-09-10 12:25:56 -07:00
zynqmp_ipi.c	Move generic ipi_mb functions to common files	2019-01-09 12:15:10 -08:00