Ravi Patel 138cde662f zynqmp: pm: Add CLK_SET_RATE_PARENT in gem clock node ... Existing implementation does not allow to change the value of the DIV1 because DIV2 does not have SET_RATE_PARENT flag. This causes DIV1 value to be fixed and only value of DIV2 will be adjusted according to required clock rate. Signed-off-by: Ravi Patel <ravi.patel@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Change-Id: Ic6c4ca091bf0c5dc91ebddf86621c82c705dc87b		2020-01-14 16:26:29 -08:00
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common	xilinx: Move IPI functions to common file	2019-01-09 12:38:00 -08:00
versal	Remove MULTI_CONSOLE_API flag and references to it	2019-06-28 10:52:48 +01:00
zynqmp	zynqmp: pm: Add CLK_SET_RATE_PARENT in gem clock node	2020-01-14 16:26:29 -08:00