Varun Wadekar 0cd6138ddc Tegra: enable processor retention and L2/CPUECTLR access ... This patch enables the processor retention and L2/CPUECTLR read/write access from the NS world only for Cortex-A57 CPUs on the Tegra SoCs. Change-Id: I9941a67686ea149cb95d80716fa1d03645325445 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>		2017-02-21 18:55:58 -08:00
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plat_psci_handlers.c	Tegra: remove support for legacy platform APIs	2015-12-04 15:41:20 -08:00
plat_secondary.c	Tegra210: lock PMC registers holding CPU vector addresses	2015-07-17 19:06:54 +05:30
plat_setup.c	Implement plat_get_syscnt_freq2 on platforms	2016-05-20 15:29:30 +01:00
plat_sip_calls.c	Tegra: SoC specific SiP handlers	2017-02-21 18:55:58 -08:00
platform_t210.mk	Tegra: enable processor retention and L2/CPUECTLR access	2017-02-21 18:55:58 -08:00