arm-trusted-firmware/drivers/arm/gic/v3
Ming Huang 5a5e0aac39 fix(gicv3): add dsb in both disable and enable function of gicv3_cpuif
A RAS error may be triggered while offline core in OS. Error:
Uncorrected software error in the Distributor, with IERR=9,SERR=f.
Core put to sleep before its Group enables were cleared.

gicv3_cpuif_disable() will be called in offline core flow.
According to GIC architecture version 3 and version 4:
Architectural execution of a DSB instruction guarantees that
the last value written to ICC_IGRPEN0_EL1, ICC_IGRPEN1_EL1,
ICC_IGRPEN1_EL3 or GICC_CTLR.{EnableGrp0, EnableGrp1}is observed
by the associated Redistributor.
An ISB or other context synchronization operation must precede
the DSB to ensure visibility of System register writes.

Signed-off-by: Ming Huang <huangming@linux.alibaba.com>
Change-Id: Iff1475657f401374c761b5e8f2f5b3a4b2040e9d
2021-07-23 10:48:00 +08:00
..
arm_gicv3_common.c Sanitise includes across codebase 2019-01-04 10:43:17 +00:00
gic-x00.c GIC-600: Fix MISRA-2012 defects 2020-07-29 16:51:05 +00:00
gic600_multichip.c GIC-600: Fix include ordering according to the coding style 2019-11-19 11:38:33 +00:00
gic600_multichip_private.h gic multichip: add support for clayton 2020-04-07 18:41:13 +05:30
gicdv3_helpers.c TF-A GICv3 driver: Add extended PPI and SPI range 2020-04-06 16:27:54 +01:00
gicrv3_helpers.c TF-A GICv3 driver: Change API for GICR_IPRIORITYR accessors 2020-04-07 18:40:44 +01:00
gicv3.mk GICv3: GIC-600: Detect GIC-600 at runtime 2020-06-09 17:05:49 +00:00
gicv3_helpers.c refactor(gicv3): use helper functions to get SPI/ESPI INTID limit 2021-06-16 09:37:14 +08:00
gicv3_main.c fix(gicv3): add dsb in both disable and enable function of gicv3_cpuif 2021-07-23 10:48:00 +08:00
gicv3_private.h refactor(gicv3): add helper function to get the limit of ESPI INTID 2021-06-16 09:24:31 +08:00