279 lines
10 KiB
C
279 lines
10 KiB
C
/*
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* Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <assert.h>
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#include <bl_common.h>
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#include <arch.h>
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#include <arch_helpers.h>
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#include <context.h>
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#include <context_mgmt.h>
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#include <cpu_data.h>
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#include <debug.h>
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#include <platform.h>
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#include <runtime_svc.h>
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#include <stddef.h>
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#include "psci_private.h"
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/*******************************************************************************
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* This function saves the power state parameter passed in the current PSCI
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* cpu_suspend call in the per-cpu data array.
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******************************************************************************/
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void psci_set_suspend_power_state(unsigned int power_state)
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{
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set_cpu_data(psci_svc_cpu_data.power_state, power_state);
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flush_cpu_data(psci_svc_cpu_data.power_state);
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}
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/*******************************************************************************
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* This function gets the power level till which the current cpu could be
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* powered down during a cpu_suspend call. Returns PSCI_INVALID_DATA if the
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* power state is invalid.
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******************************************************************************/
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int psci_get_suspend_pwrlvl(void)
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{
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unsigned int power_state;
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power_state = get_cpu_data(psci_svc_cpu_data.power_state);
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return ((power_state == PSCI_INVALID_DATA) ?
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power_state : psci_get_pstate_pwrlvl(power_state));
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}
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/*******************************************************************************
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* This function gets the state id of the current cpu from the power state
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* parameter saved in the per-cpu data array. Returns PSCI_INVALID_DATA if the
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* power state saved is invalid.
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******************************************************************************/
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int psci_get_suspend_stateid(void)
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{
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unsigned int power_state;
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power_state = get_cpu_data(psci_svc_cpu_data.power_state);
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return ((power_state == PSCI_INVALID_DATA) ?
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power_state : psci_get_pstate_id(power_state));
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}
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/*******************************************************************************
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* This function gets the state id of the cpu specified by the 'mpidr' parameter
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* from the power state parameter saved in the per-cpu data array. Returns
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* PSCI_INVALID_DATA if the power state saved is invalid.
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******************************************************************************/
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int psci_get_suspend_stateid_by_mpidr(unsigned long mpidr)
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{
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unsigned int power_state;
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power_state = get_cpu_data_by_index(plat_core_pos_by_mpidr(mpidr),
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psci_svc_cpu_data.power_state);
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return ((power_state == PSCI_INVALID_DATA) ?
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power_state : psci_get_pstate_id(power_state));
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}
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/*******************************************************************************
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* Top level handler which is called when a cpu wants to suspend its execution.
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* It is assumed that along with suspending the cpu power domain, power domains
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* at higher levels until the target power level will be suspended as well.
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* It finds the highest level where a domain has to be suspended by traversing
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* the node information and then performs generic, architectural, platform
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* setup and state management required to suspend that power domain and domains
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* below it. * e.g. For a cpu that's to be suspended, it could mean programming
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* the power controller whereas for a cluster that's to be suspended, it will
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* call the platform specific code which will disable coherency at the
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* interconnect level if the cpu is the last in the cluster and also the
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* program the power controller.
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*
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* All the required parameter checks are performed at the beginning and after
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* the state transition has been done, no further error is expected and it is
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* not possible to undo any of the actions taken beyond that point.
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******************************************************************************/
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void psci_cpu_suspend_start(entry_point_info_t *ep,
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int end_pwrlvl)
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{
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int skip_wfi = 0;
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mpidr_pwr_map_nodes_t mpidr_nodes;
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unsigned int max_phys_off_pwrlvl;
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unsigned long psci_entrypoint;
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/*
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* This function must only be called on platforms where the
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* CPU_SUSPEND platform hooks have been implemented.
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*/
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assert(psci_plat_pm_ops->pwr_domain_suspend &&
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psci_plat_pm_ops->pwr_domain_suspend_finish);
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/*
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* Collect the pointers to the nodes in the topology tree for
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* each power domain instance in the mpidr. If this function does
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* not return successfully then either the mpidr or the power
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* levels are incorrect. Either way, this an internal TF error
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* therefore assert.
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*/
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if (psci_get_pwr_map_nodes(read_mpidr_el1() & MPIDR_AFFINITY_MASK,
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MPIDR_AFFLVL0, end_pwrlvl, mpidr_nodes) != PSCI_E_SUCCESS)
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assert(0);
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/*
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* This function acquires the lock corresponding to each power
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* level so that by the time all locks are taken, the system topology
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* is snapshot and state management can be done safely.
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*/
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psci_acquire_pwr_domain_locks(MPIDR_AFFLVL0,
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end_pwrlvl,
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mpidr_nodes);
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/*
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* We check if there are any pending interrupts after the delay
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* introduced by lock contention to increase the chances of early
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* detection that a wake-up interrupt has fired.
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*/
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if (read_isr_el1()) {
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skip_wfi = 1;
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goto exit;
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}
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/*
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* Call the cpu suspend handler registered by the Secure Payload
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* Dispatcher to let it do any bookeeping. If the handler encounters an
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* error, it's expected to assert within
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*/
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if (psci_spd_pm && psci_spd_pm->svc_suspend)
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psci_spd_pm->svc_suspend(0);
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/*
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* This function updates the state of each power domain instance
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* corresponding to the mpidr in the range of power levels
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* specified.
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*/
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psci_do_state_coordination(MPIDR_AFFLVL0,
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end_pwrlvl,
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mpidr_nodes,
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PSCI_STATE_SUSPEND);
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max_phys_off_pwrlvl = psci_find_max_phys_off_pwrlvl(MPIDR_AFFLVL0,
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end_pwrlvl,
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mpidr_nodes);
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assert(max_phys_off_pwrlvl != PSCI_INVALID_DATA);
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/*
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* Store the re-entry information for the non-secure world.
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*/
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cm_init_my_context(ep);
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/* Set the secure world (EL3) re-entry point after BL1 */
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psci_entrypoint = (unsigned long) psci_cpu_suspend_finish_entry;
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/*
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* Arch. management. Perform the necessary steps to flush all
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* cpu caches.
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*/
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psci_do_pwrdown_cache_maintenance(max_phys_off_pwrlvl);
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/*
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* Plat. management: Allow the platform to perform the
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* necessary actions to turn off this cpu e.g. set the
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* platform defined mailbox with the psci entrypoint,
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* program the power controller etc.
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*/
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psci_plat_pm_ops->pwr_domain_suspend(psci_entrypoint,
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max_phys_off_pwrlvl);
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exit:
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/*
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* Release the locks corresponding to each power level in the
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* reverse order to which they were acquired.
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*/
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psci_release_pwr_domain_locks(MPIDR_AFFLVL0,
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end_pwrlvl,
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mpidr_nodes);
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if (!skip_wfi)
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psci_power_down_wfi();
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}
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/*******************************************************************************
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* The following functions finish an earlier suspend request. They
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* are called by the common finisher routine in psci_common.c.
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******************************************************************************/
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void psci_cpu_suspend_finish(pwr_map_node_t *node[], int pwrlvl)
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{
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int32_t suspend_level;
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uint64_t counter_freq;
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assert(node[pwrlvl]->level == pwrlvl);
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/* Ensure we have been woken up from a suspended state */
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assert(psci_get_state(node[MPIDR_AFFLVL0]) == PSCI_STATE_SUSPEND);
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/*
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* Plat. management: Perform the platform specific actions
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* before we change the state of the cpu e.g. enabling the
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* gic or zeroing the mailbox register. If anything goes
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* wrong then assert as there is no way to recover from this
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* situation.
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*/
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psci_plat_pm_ops->pwr_domain_suspend_finish(pwrlvl);
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/*
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* Arch. management: Enable the data cache, manage stack memory and
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* restore the stashed EL3 architectural context from the 'cpu_context'
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* structure for this cpu.
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*/
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psci_do_pwrup_cache_maintenance();
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/* Re-init the cntfrq_el0 register */
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counter_freq = plat_get_syscnt_freq();
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write_cntfrq_el0(counter_freq);
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/*
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* Call the cpu suspend finish handler registered by the Secure Payload
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* Dispatcher to let it do any bookeeping. If the handler encounters an
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* error, it's expected to assert within
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*/
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if (psci_spd_pm && psci_spd_pm->svc_suspend) {
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suspend_level = psci_get_suspend_pwrlvl();
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assert (suspend_level != PSCI_INVALID_DATA);
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psci_spd_pm->svc_suspend_finish(suspend_level);
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}
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/* Invalidate the suspend context for the node */
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psci_set_suspend_power_state(PSCI_INVALID_DATA);
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/*
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* Generic management: Now we just need to retrieve the
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* information that we had stashed away during the suspend
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* call to set this cpu on its way.
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*/
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cm_prepare_el3_exit(NON_SECURE);
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/* Clean caches before re-entering normal world */
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dcsw_op_louis(DCCSW);
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}
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