Konstantin Porotchkin 152b0e4717 marvell: drivers: Add L3/system cache management drivers ... Add LLC (L3) cache management drivers for Marvell SoCs AP806, AP807 and AP810 Change-Id: Ic70710f9bc5b6b48395d62212df7011e2fbb5894 Signed-off-by: Hanna Hawa <hannah@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>		2018-07-18 18:48:30 +03:00
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bl1	Fix MISRA rule 8.4 Part 1	2018-02-28 17:19:55 +00:00
bl2	Fix MISRA rule 8.5 in common code	2018-04-13 14:01:56 +01:00
bl2u	Fix MISRA rule 8.4 in common code	2018-02-28 17:18:46 +00:00
bl31	RAS: Allow individual interrupt registration	2018-05-04 08:33:17 +01:00
bl32	Introduce the new BL handover interface	2018-02-26 16:31:10 +00:00
common	Merge pull request #1429 from jeenu-arm/mmu-direct	2018-06-27 12:59:47 +01:00
drivers	marvell: drivers: Add L3/system cache management drivers	2018-07-18 18:48:30 +03:00
lib	lib: cpu: Add L2 cache aux control register definition to CA72	2018-07-18 18:48:30 +03:00
plat	Merge pull request #1448 from npoushin/npoushin/sgi575-coverity-fixes	2018-06-25 13:38:29 +01:00
services	Merge pull request #1437 from jeenu-arm/ras-remaining	2018-06-22 09:36:59 +01:00
tools_share	Make TF UUID RFC 4122 compliant	2018-06-14 14:41:00 +01:00