johpow01 dcbfbcb5de Workaround for Cortex A76 erratum 1800710 ... Cortex A76 erratum 1800710 is a Cat B erratum, present in older revisions of the Cortex A76 processor core. The workaround is to set a bit in the ECTLR_EL1 system register, which disables allocation of splintered pages in the L2 TLB. This errata is explained in this SDEN: https://static.docs.arm.com/sden885749/g/Arm_Cortex_A76_MP052_Software_Developer_Errata_Notice_v20.pdf Signed-off-by: John Powell <john.powell@arm.com> Change-Id: Ifc34f2e9e053dcee6a108cfb7df7ff7f497c9493		2020-06-22 17:47:54 -05:00
..
aarch32	Cortex A9:errata 794073 workaround	2019-04-12 10:10:32 +00:00
aarch64	Workaround for Cortex A76 erratum 1800710	2020-06-22 17:47:54 -05:00
cpu-ops.mk	Workaround for Cortex A76 erratum 1800710	2020-06-22 17:47:54 -05:00
errata_report.c	Coverity: remove unnecessary header file includes	2020-02-04 10:23:51 -06:00