Venkatesh Yadav Abbarapu 18e2a79f8a feat(versal): remove the time stamp configuration ... Remove the time stamp and system counter configuration, as this configuration is already done by the first stage bootloader. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> Change-Id: I41554dc2e14d97954bff299df9740a5efa30fad9		2022-03-01 21:20:21 -07:00
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aarch64	feat(versal): remove the time stamp configuration	2022-03-01 21:20:21 -07:00
include	fix(plat/xilinx/versal): resolve misra R10.3	2021-11-30 02:00:01 -08:00
pm_service	fix(plat/xilinx/versal): resolve misra R10.1 in pm services	2021-11-30 02:00:01 -08:00
bl31_versal_setup.c	feat(versal): add UART1 as console	2021-12-22 03:56:42 -07:00
plat_psci.c	fix(plat/xilinx/versal): resolve misra R14.4	2021-11-30 02:00:01 -08:00
plat_topology.c	arm64: versal: Add support for new Xilinx Versal ACAPs	2018-11-09 15:06:53 +05:30
plat_versal.c	fix(plat/xilinx/versal): resolve misra R14.4	2021-11-30 02:00:01 -08:00
platform.mk	feat(plat/versal): add support for SLS mitigation	2021-07-20 22:33:47 -06:00
sip_svc_setup.c	fix(plat/xilinx/versal): resolve misra R17.7	2021-11-30 02:00:01 -08:00
versal_gicv3.c	plat: xilinx: versal: Move versal_private.h to include directory	2020-01-15 11:01:28 -08:00
versal_ipi.c	fix(plat/xilinx/versal): resolve misra R7.2	2021-11-30 02:00:01 -08:00