David Cunado 495f3d3c51 Reset debug registers MDCR-EL3/SDCR and MDCR_EL2/HDCR ... In order to avoid unexpected traps into EL3/MON mode, this patch resets the debug registers, MDCR_EL3 and MDCR_EL2 for AArch64, and SDCR and HDCR for AArch32. MDCR_EL3/SDCR is zero'ed when EL3/MON mode is entered, at the start of BL1 and BL31/SMP_MIN. For MDCR_EL2/HDCR, this patch zero's the bits that are architecturally UNKNOWN values on reset. This is done when exiting from EL3/MON mode but only on platforms that support EL2/HYP mode but choose to exit to EL1/SVC mode. Fixes ARM-software/tf-issues#430 Change-Id: Idb992232163c072faa08892251b5626ae4c3a5b6 Signed-off-by: David Cunado <david.cunado@arm.com>		2016-11-09 15:45:06 +00:00
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aarch32	Reset debug registers MDCR-EL3/SDCR and MDCR_EL2/HDCR	2016-11-09 15:45:06 +00:00
aarch64	Reset debug registers MDCR-EL3/SDCR and MDCR_EL2/HDCR	2016-11-09 15:45:06 +00:00
tbbr	Replace all SCP FW (BL0, BL3-0) references	2015-12-14 12:31:16 +00:00
asm_macros_common.S	AArch32: Add assembly helpers	2016-08-10 12:35:46 +01:00
bl_common.h	PSCI: Introduce PSCI Library argument structure	2016-09-22 17:07:20 +01:00
debug.h	Make cpu operations warning a VERBOSE print	2016-03-22 10:00:42 +00:00
desc_image_load.h	Add new version of image loading.	2016-09-20 16:16:42 +01:00
firmware_image_package.h	Replace all SCP FW (BL0, BL3-0) references	2015-12-14 12:31:16 +00:00
runtime_svc.h	AArch32: Add API to invoke runtime service handler	2016-08-10 12:35:46 +01:00