lauwal01 2017ab241c Workaround for Neoverse N1 erratum 1165347 ... Neoverse N1 erratum 1165347 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set two bits in the implementation defined CPUACTLR2_EL1 system register. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I163d0ea00578245c1323d2340314cdc3088c450d Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>		2019-07-02 09:15:15 -05:00
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arch	arch: add some defines for generic timer registers	2019-06-17 14:03:16 +02:00
bl1	BL1: Enable pointer authentication support	2019-02-27 11:58:09 +00:00
bl2	BL2_AT_EL3: Enable pointer authentication support	2019-02-27 11:58:09 +00:00
bl2u	Standardise header guards across codebase	2018-11-08 10:20:19 +00:00
bl31	BL31: Enable pointer authentication support	2019-02-27 11:58:10 +00:00
bl32	sp_min: make sp_min_warm_entrypoint public	2019-04-25 13:37:56 +02:00
common	Add support for Branch Target Identification	2019-05-24 14:44:45 +01:00
drivers	Merge changes from topic "yg/clk_syscfg_dt" into integration	2019-06-19 15:06:00 +00:00
dt-bindings	stm32mp1: update device tree files	2019-01-18 15:45:08 +01:00
lib	Workaround for Neoverse N1 erratum 1165347	2019-07-02 09:15:15 -05:00
plat	Add option for defining platform DRAM2 base	2019-05-15 11:42:39 +01:00
services	Remove support for the SMC Calling Convention 2.0	2019-01-30 16:01:49 +00:00
tools_share	Sanitise includes across codebase	2019-01-04 10:43:17 +00:00