20fdf0b05c
CLK_TOPSW_LSBUS is parent of WDT clock. Clock from invalid clock list would not be registered to CCF framework and so cannot be used as parent of other clocks. WDT clock has default parent as CLK_TOPSW_LSBUS(APB clock). If CLK_TOPSW_LSBUS is not registered, CCF would not recognize that clock and hence rate of WDT clock would be calculated to be 0 by CCF(as parent rate is considered 0). So it is necessary to allow registration of CLK_TOPSW_LSBUS clock. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Change-Id: Iceaba0f137784fc5fd666e66ffc4c143381c6ccc |
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