arm-trusted-firmware/drivers/arm
Andre Przywara 79d89e3da0 drivers: arm: gicv3: Allow detecting number of cores
A GICv3 interrupt controller will be instantiated for a certain number
of cores. This will result in the respective number of GICR frames. The
last frame will have the "Last" bit set in its GICR_TYPER register.

For platforms with a topology unknown at build time (the Arm FPGAs, for
instance), we need to learn the number of used cores at runtime, to size
the GICR region in the devicetree accordingly.

Add a generic function that iterates over all GICR frames until it
encounters one with the "Last" bit set. It returns the number of cores
the GICv3 has been configured for.

Change-Id: I79f033c50dfc1c275aba7122725868811abcc4f8
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2020-09-29 13:28:25 +01:00
..
cci Sanitise includes across codebase 2019-01-04 10:43:17 +00:00
ccn Coverity: remove unnecessary header file includes 2020-02-04 10:23:51 -06:00
css fconf: Clean confused naming between TB_FW and FW_CONFIG 2020-06-24 08:44:26 +01:00
fvp fvp: pwrc: Move to drivers/ folder 2019-01-25 16:04:11 +00:00
gic drivers: arm: gicv3: Allow detecting number of cores 2020-09-29 13:28:25 +01:00
pl011 pl011: Use generic console_t data structure 2020-02-25 09:34:38 +00:00
pl061 Sanitise includes across codebase 2019-01-04 10:43:17 +00:00
sbsa libc: Consolidate unified definitions 2019-12-06 11:37:19 +01:00
scu drivers: add a driver for snoop control unit 2020-01-03 10:44:28 +00:00
smmu SMMUv3:Changed retry loop to delay timer(GENFW-3329) 2019-11-01 10:51:07 -06:00
sp804 Remove several warnings reported with W=2 2019-04-01 10:43:42 +01:00
sp805 Sanitise includes across codebase 2019-01-04 10:43:17 +00:00
tzc TZ DMC620 driver: Fix MISRA-2012 defects 2020-07-27 15:04:14 +01:00