8cfc3fd295
On a GICv2 system, the group status of PPIs and SGIs is set in the GICD_IGROUPR0 register. On a GICv3 system, if affinity routing is enabled for the non-secure state, then the group status of PPIs and SGIs should be set in the GICR_IGROUPR0 register. ARM Trusted firmware sets the group status using the GICv2 sequence. On a GICv3 system, if the group status of an interrupt is set to Group 1 through a write to the GICD_IGROUPR0, then the GICR_IGROUPR0 is updated as well. The current sequence is incorrect since it first marks all PPIs and SGIs as Group 1. It then clears the bits in GICD_IGROUPR0 corresponding to secure interrupts to set their group status to Group 0. This operation is a no-op. It leaves the secure generic timer interrupt (#29) used by the TSP marked as Group 1. This causes the interrupt to interfere with the execution of non-secure software. Once an interrupt has been marked as Group 1, the GICR_IGROUPR0 should be programmed to change its group status. This patch rectifies this issue by setting the group status of only the non-secure PPI and SGIs to Group 1 in the first place. GICD_IGROUPR0 resets to 0. So secure interrupts are marked as Group 0 by default. Change-Id: I958b4b15f3e2b2444ce4c17764def36216498d00 |
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| .. | ||
| arm_gic.c | ||
| gic_v2.c | ||
| gic_v3.c | ||