142 lines
5.5 KiB
C
142 lines
5.5 KiB
C
/*
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* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch_helpers.h>
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#include <assert.h>
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#include <bl_common.h>
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#include <debug.h>
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#include <console.h>
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#include <mmio.h>
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#include <platform.h>
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#include <platform_def.h>
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#include "../../bl1/bl1_private.h"
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#include "fvp_def.h"
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#include "fvp_private.h"
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#if USE_COHERENT_MEM
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/*******************************************************************************
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* Declarations of linker defined symbols which will help us find the layout
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* of trusted SRAM
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******************************************************************************/
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extern unsigned long __COHERENT_RAM_START__;
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extern unsigned long __COHERENT_RAM_END__;
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/*
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* The next 2 constants identify the extents of the coherent memory region.
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* These addresses are used by the MMU setup code and therefore they must be
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* page-aligned. It is the responsibility of the linker script to ensure that
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* __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
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* page-aligned addresses.
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*/
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#define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
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#define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
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#endif
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/* Data structure which holds the extents of the trusted SRAM for BL1*/
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static meminfo_t bl1_tzram_layout;
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meminfo_t *bl1_plat_sec_mem_layout(void)
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{
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return &bl1_tzram_layout;
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}
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/*******************************************************************************
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* Perform any BL1 specific platform actions.
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******************************************************************************/
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void bl1_early_platform_setup(void)
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{
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const size_t bl1_size = BL1_RAM_LIMIT - BL1_RAM_BASE;
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/* Initialize the console to provide early debug support */
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console_init(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, PL011_BAUDRATE);
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/* Allow BL1 to see the whole Trusted RAM */
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bl1_tzram_layout.total_base = FVP_TRUSTED_SRAM_BASE;
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bl1_tzram_layout.total_size = FVP_TRUSTED_SRAM_SIZE;
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/* Calculate how much RAM BL1 is using and how much remains free */
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bl1_tzram_layout.free_base = FVP_TRUSTED_SRAM_BASE;
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bl1_tzram_layout.free_size = FVP_TRUSTED_SRAM_SIZE;
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reserve_mem(&bl1_tzram_layout.free_base,
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&bl1_tzram_layout.free_size,
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BL1_RAM_BASE,
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bl1_size);
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/* Initialize the platform config for future decision making */
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fvp_config_setup();
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}
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/*******************************************************************************
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* Function which will evaluate how much of the trusted ram has been gobbled
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* up by BL1 and return the base and size of whats available for loading BL2.
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* Its called after coherency and the MMU have been turned on.
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******************************************************************************/
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void bl1_platform_setup(void)
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{
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/* Initialise the IO layer and register platform IO devices */
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fvp_io_setup();
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}
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/*******************************************************************************
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* Perform the very early platform specific architecture setup here. At the
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* moment this only does basic initialization. Later architectural setup
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* (bl1_arch_setup()) does not do anything platform specific.
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******************************************************************************/
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void bl1_plat_arch_setup(void)
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{
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fvp_cci_init();
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fvp_cci_enable();
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fvp_configure_mmu_el3(bl1_tzram_layout.total_base,
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bl1_tzram_layout.total_size,
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BL1_RO_BASE,
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BL1_RO_LIMIT
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#if USE_COHERENT_MEM
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, BL1_COHERENT_RAM_BASE,
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BL1_COHERENT_RAM_LIMIT
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#endif
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);
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}
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/*******************************************************************************
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* Before calling this function BL2 is loaded in memory and its entrypoint
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* is set by load_image. This is a placeholder for the platform to change
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* the entrypoint of BL2 and set SPSR and security state.
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* On FVP we are only setting the security state, entrypoint
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******************************************************************************/
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void bl1_plat_set_bl2_ep_info(image_info_t *bl2_image,
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entry_point_info_t *bl2_ep)
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{
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SET_SECURITY_STATE(bl2_ep->h.attr, SECURE);
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bl2_ep->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
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}
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