Varun Wadekar 7d74487c2a Tegra186: store TZDRAM base/size to scratch registers ... This patch saves the TZDRAM base and size values to secure scratch registers, for the WB0. The WB0 reads these values and uses them to verify integrity of the TZDRAM aperture. Change-Id: Ic70914cb958249f06cb58025a24d13734a85e16e Signed-off-by: Jeetesh Burman <jburman@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>		2020-03-09 15:25:16 -07:00
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drivers	Tegra186: add SE support to generate SHA256 of TZRAM	2020-03-09 15:25:16 -07:00
plat_memctrl.c	Tegra186: store TZDRAM base/size to scratch registers	2020-03-09 15:25:16 -07:00
plat_psci_handlers.c	Tegra186: add SE support to generate SHA256 of TZRAM	2020-03-09 15:25:16 -07:00
plat_secondary.c	Tegra: rename secure scratch register macros	2019-01-23 10:32:48 -08:00
plat_setup.c	Tegra186: add support for bpmp_ipc driver	2020-03-09 15:25:16 -07:00
plat_sip_calls.c	Tegra186: sip_calls: fix defects flagged by MISRA scan	2019-01-18 09:09:15 -08:00
plat_smmu.c	Tegra186: smmu: add support for backup multiple smmu regs	2019-01-31 08:45:22 -08:00
plat_trampoline.S	Tegra186: trampoline: include bl_common.h	2019-02-07 08:47:51 -08:00
platform_t186.mk	Tegra186: add SE support to generate SHA256 of TZRAM	2020-03-09 15:25:16 -07:00