48d6b26434
We previously left our caches on during power-down to prevent any non-caching accesses to memory that is cached by other cores. Now with the last accessed areas all being marked as non-cached by USE_COHERENT_MEM we can rely on that to workaround our interconnect issues. Remove the old workaround. Change-Id: Idadb7696d1449499d1edff4f6f62ab3b99d1efb7 Signed-off-by: Andrew F. Davis <afd@ti.com> |
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| board/generic | ||
| common | ||
| include | ||
| platform.mk | ||