We previously left our caches on during power-down to prevent any non-caching accesses to memory that is cached by other cores. Now with the last accessed areas all being marked as non-cached by USE_COHERENT_MEM we can rely on that to workaround our interconnect issues. Remove the old workaround. Change-Id: Idadb7696d1449499d1edff4f6f62ab3b99d1efb7 Signed-off-by: Andrew F. Davis <afd@ti.com> |
||
---|---|---|
.. | ||
drivers | ||
k3_bl31_setup.c | ||
k3_console.c | ||
k3_gicv3.c | ||
k3_helpers.S | ||
k3_psci.c | ||
k3_topology.c | ||
plat_common.mk |