Loh Tien Hock 51f366ac85 plat: intel: Fix faulty DDR calibration value ... A DDR calibration value is missing write mask, causing ECC DDR calibration to fail. This patch addresses the issue. ECC should also be scrubbed before MMU initializes, thus the scrubbing is moved to ddr intialization phase. Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>		2019-02-13 14:39:31 +08:00
..
soc/stratix10	plat: intel: Fix faulty DDR calibration value	2019-02-13 14:39:31 +08:00